US3701145A
Expired / Lapsed
US
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Analog to digital converter
Assignee: Honeywell Inc
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Filing: 1970-11-04
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Granted: 1972-10-24
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Expires: 1990-11-04
Abstract
Abstract An integrating analog to digital conversion apparatus includes means whereby a non-linear input variable is time integrated for a fixed period of time. A fixed reference source of opposite polarity to said input variable is then time integrated for a variable second period of time. The second variable time period being registered in a digital pulse counter, whereby the digital output of the counter at the termination of the second time period is representative of the value of the input variable. The apparatus includes addressable memory means having stored therein digital correction data, control network means for transferring digital data between elements of the apparatus, arithmetic means for modifying, in singular bit fashion, the digital output of the pulse counter in order to effect digital linearization of the non-linear input variable. Secondary counter means operationally stores within itself the resultant modified singular data bits, whereby the digital output of the secondary counter means is representative of the linearized value of the non-linear input variable.
Inventors
- 👤 William P Bergin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:59
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/58; H03M1/52
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
819 words
An integrating analog to digital converter for providing a linearized digital representation of an analog input signal which is a nonlinear representation of a primary variable, said converter comprising; pulse generating means for generating a series of equally time spaced pulses; pulse counter means for producing a digital output representative of the number of pulses applied to its input; control gating means for selectively connecting the output of said pulse generating means to the input of said pulse counter means; integrating means for generating an output signal representative of the time integral of the input signals applied thereto; switching means for applying an analog input signal to said integrating means to produce a first integrated output signal; comparator means responsively coupled to said integrating means for actuating said control gating means whereby initiating transmission of pulses from said pulse generating means to the input of said pulse counter means at the beginning of said integration of said first input signal; said counter means being driven from a predetermined starting count to a full scale count in a first time interval beginning at the time said first intEgrated output signal is at a threshold level, said first integrating output signal varying from said threshold level to a second level during said first time interval; means responsive to a full scale count in said counter means for actuating said switching means to apply a second, or reference, signal to said integrating means, said reference signal being of opposite polarity with respect to said analog input signal; said integrating means being operative to produce a second integrated output signal in response to said second signal varying from said second level to said threshold level during a second time interval immediately following said first time interval; said comparator means coupled to said integrating means being further responsive to the return of said second integrated signal to said threshold value for actuating said control gate means for terminating transmission of pulses from said pulse generating means to said counter means at the termination of said second time interval whereby said digital output of said pulse counter means at the end of said second time interval is representative of the value of said analog input signal; linearizing means comprising addressable memory means having a plurality of data correction words addressably stored therein; means responsive to said digital output of said pulse counter means for addressing said memory means for selecting a corresponding one of said data correction words; arithmetic means responsive to said digital output of said pulse counter means and of said selected data correction word for modifying said digital output in accordance with said data correction word; and output storage means capable of having stored therein the modified digital output of said arithmetic means and being operative to provide a linearized representation of said primary variable, said arithmetic means for modifying said digital output of said pulse counter also including control signal generator means for generating a plurality of control signals; control network means coupled to said control signal generator means and responsive to said control signal for effecting a predetermined sequential transfer of data in singular bit order; said control network means including a first, a second, and a third control network; said first control network being connected between said digital output of said pulse counter means and said arithmetic means for effecting the transfer of output signals from said digital output of said pulse counter means to an input of said arithmetic means under the control of said control signals from said control signal generator means; said second control network being connected between said addressable memory means and said arithmetic emans for effecting the transfer of a selected one of said data correction words from said addressable memory means to an input of said arithmetic means under the control of said control signals from said control signal generator; said data correction words each comprising a plurality of data correction bits, the first bit of each data correction word being a sign bit, said addressable memory means having an output comprising a plurality of digital output signals consisting of said data correction bits; and buffer storage means; said third control network being connected between said arithmetic means and said output storage means for effecting the transfer of output signals from said arithmetic means to the input of said output storage means under the control of said control signal generator; said buffer storage means being connected between an output of said third control network and an input of said arithmetic means, said arithmetic means including means for producing, in addition to the modified data signal, a carry-or-borrow sign, said carry-or-borrow signal being transferred to and stored for subsequent use in said buffer storage means; said output storage means providing output signals comprising a digital representation of the daTa stored therein, said stored data being representative of the value of the linearized primary variable.
Claim 2
Dependent Claim
819 words
An integrating analog to digital converter for providing a linearized digital representation of an analog input signal which is a nonlinear representation of a primary variable, said converter comprising; pulse generating means for generating a series of equally time spaced pulses; pulse counter means for producing a digital output representative of the number of pulses applied to its input; control gating means for selectively connecting the output of said pulse generating means to the input of said pulse counter means; integrating means for generating an output signal representative of the time integral of the input signals applied thereto; switching means for applying an analog input signal to said integrating means to produce a first integrated output signal; comparator means responsively coupled to said integrating means for actuating said control gating means whereby initiating transmission of pulses from said pulse generating means to the input of said pulse counter means at the beginning of said integration of said first input signal; said counter means being driven from a predetermined starting count to a full scale count in a first time interval beginning at the time said first intEgrated output signal is at a threshold level, said first integrating output signal varying from said threshold level to a second level during said first time interval; means responsive to a full scale count in said counter means for actuating said switching means to apply a second, or reference, signal to said integrating means, said reference signal being of opposite polarity with respect to said analog input signal; said integrating means being operative to produce a second integrated output signal in response to said second signal varying from said second level to said threshold level during a second time interval immediately following said first time interval; said comparator means coupled to said integrating means being further responsive to the return of said second integrated signal to said threshold value for actuating said control gate means for terminating transmission of pulses from said pulse generating means to said counter means at the termination of said second time interval whereby said digital output of said pulse counter means at the end of said second time interval is representative of the value of said analog input signal; linearizing means comprising addressable memory means having a plurality of data correction words addressably stored therein; means responsive to said digital output of said pulse counter means for addressing said memory means for selecting a corresponding one of said data correction words; arithmetic means responsive to said digital output of said pulse counter means and of said selected data correction word for modifying said digital output in accordance with said data correction word; and output storage means capable of having stored therein the modified digital output of said arithmetic means and being operative to provide a linearized representation of said primary variable, said arithmetic means for modifying said digital output of said pulse counter also including control signal generator means for generating a plurality of control signals; control network means coupled to said control signal generator means and responsive to said control signal for effecting a predetermined sequential transfer of data in singular bit order; said control network means including a first, a second, and a third control network; said first control network being connected between said digital output of said pulse counter means and said arithmetic means for effecting the transfer of output signals from said digital output of said pulse counter means to an input of said arithmetic means under the control of said control signals from said control signal generator means; said second control network being connected between said addressable memory means and said arithmetic emans for effecting the transfer of a selected one of said data correction words from said addressable memory means to an input of said arithmetic means under the control of said control signals from said control signal generator; said data correction words each comprising a plurality of data correction bits, the first bit of each data correction word being a sign bit, said addressable memory means having an output comprising a plurality of digital output signals consisting of said data correction bits; and buffer storage means; said third control network being connected between said arithmetic means and said output storage means for effecting the transfer of output signals from said arithmetic means to the input of said output storage means under the control of said control signal generator; said buffer storage means being connected between an output of said third control network and an input of said arithmetic means, said arithmetic means including means for producing, in addition to the modified data signal, a carry-or-borrow sign, said carry-or-borrow signal being transferred to and stored for subsequent use in said buffer storage means; said output storage means providing output signals comprising a digital representation of the daTa stored therein, said stored data being representative of the value of the linearized primary variable.
Claim 3
Dependent Claim
36 words
An integrating analog-to-digital converter as set forth in claim 1 wherein said arithmetic means comprises a one bit adder/subtractor; said arithmetic means including means operable to selectively add-or-subtract depending upon the instruction of said sign bit.
Claim 4
Dependent Claim
52 words
An integrating analog-to-digital converter as set forth in claim 1 wherein said output storage means comprises a binary counter being operative to produce a binary digital output signal representative of the number of pulses applied to its input, said output signal being representative of the binary value of the linearized primary variable.
Claim 5
Dependent Claim
53 words
An integrating analog-to-digital converter as set forth in claim 3 including binary-to-BCD control means being operative to include said binary digital output signals into binary coded decimal form, BCD counter means comprising a plurality of flip-flops being operative to store therein the resultant bit data of said output storage means in BCD format.
Claim 6
Dependent Claim
72 words
An integrating analog-to-digital converter as set forth in claim 4 wherein said binary-to-BCD control means comprises means operative to condition said binary counter to count down to zero in binary format and, simultaneously, to further condition said BCD counter to count from zero in BCD format, said BCD format at the time said binary counter has reached said zero count, constituting a digital representation of a linearized characterization of said input signal.
Claim 7
Dependent Claim
44 words
An integrating analog-to-digital converter as set forth in claim 5 including an indicator, said indicator comprising means operative to provide a visual decimal display of said BCD format, said visual decimal display constituting a visual representation of a linearized characterization of said input signal.
Claim 8
Dependent Claim
669 words
An integrating analog to digital converter for providing a linearized digital representation of an analog input signal which is a nonlinear representation of a primary variable, said converter comprising; pulse generating means for generating a series of equally time spaced pulses; pulse counter means for producing a digital output representative of the number of pulses applied to its input; control gating means for selectively connecting the output of said pulse generating means to the input of said pulse counter means; integrating means for generating an output signal representative of the time integral of the input signals applied thereto; switching means for applying an analog input signal to said integrating means to produce a first integrated output signal; comparator means responsively coupled to said integrating means for actuating said control gating means whereby initiating transmission of pulses from said pulse generating means to the input of said pulse counter means at the beginning of said integration of said first input signal; said counter means being driven from a predetermined starting count to a full scale count in a first time interval beginning at the time said first integrated output signal is at a threshold level, said first integrated output signal varying from said threshold level to a second level during said first time interval; means responsive to a full scale count in said counter means for actuating said switching means to apply a second, or reference, signal to said integrating means, said reference signal being of opposite polarity with respect to said analog input signal; said integrating means being operative to produce a second integrated output signal in response to said second signal varying from said second level to said threshold level during a second time interval immediately following said first time interval; said comparator means coupled to said integrating means being further responsive to the return of said second integrated signal to said threshold value for actuating said control gate means for terminating transmission of pulses from saiD pulse generating means to said counter means at the termination of said second time interval whereby said digital output of said pulse counter means at the end of said second time interval is representative of the value of said analog input signal; linearizing means comprising addressable memory means having a plurality of data correction words addressably stored therein; means responsive to said digital output of said pulse counter means for addressing said memory means for selecting a corresponding one of said data correction words; arithmetic means responsive to said digital output of said pulse counter means and of said selected data correction word for modifying said digital output in accordance with said data correction word; output storage means capable of having stored therein the modified digital output of said arithmetic means and being operative to provide a linearized representation of said primary variable, said linearizing means including input signal means, said input signal means for said linearizing means includes said pulse counter means; said pulse counter means comprising a binary counter consisting of (M + N) flip-flops, where M and N are any positive whole integers excluding zero, each of said (M + N) flip-flops having stored therein a data bit representative of one of the binary states, said stored data bits constituting a digital representation of a nonlinearized process variable, said stored data bits also being value weighted as M most significant bits and N least significant bits; said addressable memory having an address capability of 2M combinations, said combinations each having at its address location one of said data correction words, each of said data correction words comprising a plurality of data correction bits, the value of said data correction bits being constant over a range of 2N consecutive states of said binary counter, said data correction bits being arranged in a predetermined sequence consisting of a sign bit in the first sequential position consecutively followed by the remainder of the data correction word beginning with the least significant data bit and ending with the most significant data bit.
Claim 9
Dependent Claim
669 words
An integrating analog to digital converter for providing a linearized digital representation of an analog input signal which is a nonlinear representation of a primary variable, said converter comprising; pulse generating means for generating a series of equally time spaced pulses; pulse counter means for producing a digital output representative of the number of pulses applied to its input; control gating means for selectively connecting the output of said pulse generating means to the input of said pulse counter means; integrating means for generating an output signal representative of the time integral of the input signals applied thereto; switching means for applying an analog input signal to said integrating means to produce a first integrated output signal; comparator means responsively coupled to said integrating means for actuating said control gating means whereby initiating transmission of pulses from said pulse generating means to the input of said pulse counter means at the beginning of said integration of said first input signal; said counter means being driven from a predetermined starting count to a full scale count in a first time interval beginning at the time said first integrated output signal is at a threshold level, said first integrated output signal varying from said threshold level to a second level during said first time interval; means responsive to a full scale count in said counter means for actuating said switching means to apply a second, or reference, signal to said integrating means, said reference signal being of opposite polarity with respect to said analog input signal; said integrating means being operative to produce a second integrated output signal in response to said second signal varying from said second level to said threshold level during a second time interval immediately following said first time interval; said comparator means coupled to said integrating means being further responsive to the return of said second integrated signal to said threshold value for actuating said control gate means for terminating transmission of pulses from saiD pulse generating means to said counter means at the termination of said second time interval whereby said digital output of said pulse counter means at the end of said second time interval is representative of the value of said analog input signal; linearizing means comprising addressable memory means having a plurality of data correction words addressably stored therein; means responsive to said digital output of said pulse counter means for addressing said memory means for selecting a corresponding one of said data correction words; arithmetic means responsive to said digital output of said pulse counter means and of said selected data correction word for modifying said digital output in accordance with said data correction word; output storage means capable of having stored therein the modified digital output of said arithmetic means and being operative to provide a linearized representation of said primary variable, said linearizing means including input signal means, said input signal means for said linearizing means includes said pulse counter means; said pulse counter means comprising a binary counter consisting of (M + N) flip-flops, where M and N are any positive whole integers excluding zero, each of said (M + N) flip-flops having stored therein a data bit representative of one of the binary states, said stored data bits constituting a digital representation of a nonlinearized process variable, said stored data bits also being value weighted as M most significant bits and N least significant bits; said addressable memory having an address capability of 2M combinations, said combinations each having at its address location one of said data correction words, each of said data correction words comprising a plurality of data correction bits, the value of said data correction bits being constant over a range of 2N consecutive states of said binary counter, said data correction bits being arranged in a predetermined sequence consisting of a sign bit in the first sequential position consecutively followed by the remainder of the data correction word beginning with the least significant data bit and ending with the most significant data bit.
Claim 10
Dependent Claim
529 words
A digital linearizing system, said system including input signal means, said input signal means comprising a binary counter consisting of (M + N) flip-flops, where M and N are any positive whole integers excluding zero, each of said (M + N) flip-flops having stored therein a data bit representing one of the binary states, said stored data bits constituting a digital representation of a nonlinearized analog input variable, said stored data bits being value weighted as M most significant data bits and N least significant data bits, storage means consisting of an addressable memory, said memory having an address capability of 2M combinations, said combinations each having at its address location a data correction word, said data correction word comprising a plurality of data correction bits, the value of said data correction bits being constant over a range of 2N consecutive states of said binary counter, said data correction bits also being arranged in a predetermined sequence consisting of a sign bit in the first sequential position consecutively followed by the remainder of the data correction word beginning with the least significant data bit and ending with the most significant data bit, signal responsive means by which the memory is addressed by the M most significant output signals from said binary counter, arithmetic means for effecting the arithmetic modification of said nonlinearized input variable, control signal generator means for producing a plurality of sequentially spaced control pulses, control network means coupled to said control signal generator means and being responsive to said control pulses for effecting A predetermined sequential transfer of data in singular bit order; said control network means including a first, a second and a third control network; said first control network being responsive to a first one of said control pulses for connecting the output of said binary counter to the input of said arithmetic means, said first control network means being operative under control of said first of said control pulses to transfer the data bits stored in said binary counter to said arithmetic means; second control network responsive to a second one of said control pulses for connecting the output of said addressable memory to the input of said arithmetic means, said second control network being operative under control of said second of said control pulses to transfer the data correction bits stored in said addressable memory to said arithmetic means; third control network responsive to a third one of said control pulses for connecting an output of said arithmetic means to the input of an output storage means, said third control network means being operative under control of said third of said control pulses to transfer the sum-or-difference data bit stored within said arithmetic means to said output storage means; buffer storage means being connected between an output of said third control network and an input of said arithmetic means, said arithmetic means including means for producing, in addition to the modified data signal, a carry-or-borrow signal, said carry-or-borrow signal being transferred to and stored for subsequent use in said buffer storage means; said output storage means having a digital output representative of the value of a linearized characterization of said input signal.
Claim 11
Dependent Claim
529 words
A digital linearizing system, said system including input signal means, said input signal means comprising a binary counter consisting of (M + N) flip-flops, where M and N are any positive whole integers excluding zero, each of said (M + N) flip-flops having stored therein a data bit representing one of the binary states, said stored data bits constituting a digital representation of a nonlinearized analog input variable, said stored data bits being value weighted as M most significant data bits and N least significant data bits, storage means consisting of an addressable memory, said memory having an address capability of 2M combinations, said combinations each having at its address location a data correction word, said data correction word comprising a plurality of data correction bits, the value of said data correction bits being constant over a range of 2N consecutive states of said binary counter, said data correction bits also being arranged in a predetermined sequence consisting of a sign bit in the first sequential position consecutively followed by the remainder of the data correction word beginning with the least significant data bit and ending with the most significant data bit, signal responsive means by which the memory is addressed by the M most significant output signals from said binary counter, arithmetic means for effecting the arithmetic modification of said nonlinearized input variable, control signal generator means for producing a plurality of sequentially spaced control pulses, control network means coupled to said control signal generator means and being responsive to said control pulses for effecting A predetermined sequential transfer of data in singular bit order; said control network means including a first, a second and a third control network; said first control network being responsive to a first one of said control pulses for connecting the output of said binary counter to the input of said arithmetic means, said first control network means being operative under control of said first of said control pulses to transfer the data bits stored in said binary counter to said arithmetic means; second control network responsive to a second one of said control pulses for connecting the output of said addressable memory to the input of said arithmetic means, said second control network being operative under control of said second of said control pulses to transfer the data correction bits stored in said addressable memory to said arithmetic means; third control network responsive to a third one of said control pulses for connecting an output of said arithmetic means to the input of an output storage means, said third control network means being operative under control of said third of said control pulses to transfer the sum-or-difference data bit stored within said arithmetic means to said output storage means; buffer storage means being connected between an output of said third control network and an input of said arithmetic means, said arithmetic means including means for producing, in addition to the modified data signal, a carry-or-borrow signal, said carry-or-borrow signal being transferred to and stored for subsequent use in said buffer storage means; said output storage means having a digital output representative of the value of a linearized characterization of said input signal.
Claim 12
Dependent Claim
35 words
A digital linearizing system as set forth in claim 8 wherein said arithmetic means comprises a one-bit adder/subtractor; said arithmetic means including means operable to selectively add-or-subtract depending upon the instruction of said sign bit.
Claim 13
Dependent Claim
36 words
A digital linearizing system as set forth in claim 8 wherein said output storage means comprises a binary counter of (M+N) flip-flops, each of said flip-flops comprising means for storing individual ones of said reluctant bits.
Claim 14
Dependent Claim
53 words
A digital linearizing system as set forth in claim 10 including binary to BCD control means wherein data bits of binary form are encoded into binary coded decimal form, BCD counter means comprising a plurality of flip-flops sufficient to store therein the resultant bit data of said output storage means in BCD format.
Claim 15
Dependent Claim
77 words
A digital linearizing system as set forth in claim 11 wherein said binary to BCD control means comprises means operative to condition said binary counter to count down to zero in binary format and also comprises means operative to condition said BCD counter to count up from zero in BCD format, said BCD format at the time said binary counter has reached said zero count, constituting a digital representation of a linearized characterization of said input signal.
Claim 16
Dependent Claim
521 words
A linearizing analog to digital converter for providing a linearized digital representation of an analog input signal which is a nonlinear representation of a primary variable, said converter comprising input terminal means arranged to be connected to a source of an analog input signal, analog to digital converter means including a pulse counter means for producing a digital output representative of the digital value of said analog input signal; linearizing means comprising addressable memory means having a plurality of data correction words addressably stored therein; means responsive to said digital output of said pulse counter means for addressing said memory means for selecting a corresponding one of said data correction words; arithmetic means responsive to said digital output of said pulse counter means and of said selected data correction word for modifying said digital output in accordance with said data correction word; and output storage means capable of hAving stored therein the modified digital output of said arithmetic means being operative to provide a linearized representation of said primary variable, said arithmetic means for modifying said digital output of said counter means also includes control signal generator means for generating a plurality of control signals; control network means coupled to said control signal generator means and responsive to said control signal for effecting a predetermined sequential transfer of data in singular bit order; said control network means including a first, a second, and a third control network; said first control network being connected between said digital output of said pulse counter means and said arithmetic means for effecting the transfer of output signals from said digital output of said pulse counter means to an input of said arithmetic means under the control of said control signals from said control signal generator means; said second control network being connected between said addressable memory means and said arithmetic means for effecting the transfer of a selected one of said data correction words from said addressable memory means to an input of said arithmetic means under the control of said control signals from said control signal generator; said data correction words each comprising a plurality of data correction bits, the first bit of each data correction word being a sign bit, said addressable memory means having an output comprising a plurality of digital output signal consisting of said data correction bits; and buffer storage means; said third control network being connected between said arithmetic means and said output storage means for effecting the transfer of output signals from said arithmetic means to the input of said output storage means under the control of said control signals from said control signal generator; said buffer storage means being connected between an output of said third control network and an input of said arithmetic means, said arithmetic means including means for producing, in addition to the modified data signal, a carry-or-borrow signal, said carry-or-borrow signal being transferred to and stored for subsequent use in said buffer storage means; said output storage means providing output signals comprising a digital representation of the data stored therein, said stored data being representative of the value of the linearized primary variable.
Claim 17
Dependent Claim
521 words
A linearizing analog to digital converter for providing a linearized digital representation of an analog input signal which is a nonlinear representation of a primary variable, said converter comprising input terminal means arranged to be connected to a source of an analog input signal, analog to digital converter means including a pulse counter means for producing a digital output representative of the digital value of said analog input signal; linearizing means comprising addressable memory means having a plurality of data correction words addressably stored therein; means responsive to said digital output of said pulse counter means for addressing said memory means for selecting a corresponding one of said data correction words; arithmetic means responsive to said digital output of said pulse counter means and of said selected data correction word for modifying said digital output in accordance with said data correction word; and output storage means capable of hAving stored therein the modified digital output of said arithmetic means being operative to provide a linearized representation of said primary variable, said arithmetic means for modifying said digital output of said counter means also includes control signal generator means for generating a plurality of control signals; control network means coupled to said control signal generator means and responsive to said control signal for effecting a predetermined sequential transfer of data in singular bit order; said control network means including a first, a second, and a third control network; said first control network being connected between said digital output of said pulse counter means and said arithmetic means for effecting the transfer of output signals from said digital output of said pulse counter means to an input of said arithmetic means under the control of said control signals from said control signal generator means; said second control network being connected between said addressable memory means and said arithmetic means for effecting the transfer of a selected one of said data correction words from said addressable memory means to an input of said arithmetic means under the control of said control signals from said control signal generator; said data correction words each comprising a plurality of data correction bits, the first bit of each data correction word being a sign bit, said addressable memory means having an output comprising a plurality of digital output signal consisting of said data correction bits; and buffer storage means; said third control network being connected between said arithmetic means and said output storage means for effecting the transfer of output signals from said arithmetic means to the input of said output storage means under the control of said control signals from said control signal generator; said buffer storage means being connected between an output of said third control network and an input of said arithmetic means, said arithmetic means including means for producing, in addition to the modified data signal, a carry-or-borrow signal, said carry-or-borrow signal being transferred to and stored for subsequent use in said buffer storage means; said output storage means providing output signals comprising a digital representation of the data stored therein, said stored data being representative of the value of the linearized primary variable.
Claim 18
Dependent Claim
43 words
A linearizing analog to digital converter as set forth in claim 13 wherein said arithmetic means includes a one bit adder/subtracter, and means operable to control said one bit adder/subtracter to selectively add or subtract depending upon the instruction of said sign bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |