Digital to analog converter

Claim 2

In a converter for providing an analog output signal corresponding to a digital input code, comprising: voltage divider means for providing a step voltage selected between first and second reference voltages in response to the digital input code, comprising: resistance means coupled between the first and second reference voltages, for developing on each of a rank ordered plurality of step nodes a predetermined step voltage between the first and second reference voltages; and R ladder switching means coupled between the resistance means and a common rail, for coupling, in response to the digital input code, a selected one of the step nodes to the common rail; and charge redistribution means coupled to the common rail, for providing the analog output signal as a function of the step voltage on the common rail and the digital input code, comprising: capacitance means comprising a rank ordered plurality of capacitors having respective first plates and interconnected second plates, for developing the analog output signal on the second plates as a function of the voltages coupled to the first plates, wherein the improvement comprises: C ladder switching means having a rank ordered plurality of C rung switching elements and a rank ordered plurality of C rail switching elements coupled to the first and second reference voltages, the common rail and each of the first plates of the capacitors, for coupling, in response to the digital input code, the step voltage on the common rail to the first plate of a selected one of the capacitors, the first reference voltage to the first plates of each of the capacitors of lower rank than the selected one of the capacitors, and the second reference voltage to the first plates of each of the capacitors of higher rank than the selected one of the capacitors.

Claim 3

A converter for providing an analog output signal corresponding to a digital input code, comprising: voltage divider means for providing a step voltage selected between first and second reference voltages in response to the digital input code, comprising: resistance means coupled between the first and second reference voltages, for developing on each of a plurality of step nodes a predetermined step voltage between the first and second reference voltages; R ladder switching means coupled between the resistance means and a common rail, for coupling, in response to the digital code, a selected one of the step nodes to the common rail; and charge redistribution means coupled to the common rail, for providing the analog output signal as a function of the step voltage on the common rail and the digital input code, comprising: capacitance means comprising a rank ordered plurality of capacitors having respective first plates and interconnected second plates, for developing the analog output signal on the second plates as a function of the voltages coupled to the first plates; a C rung switching network comprising a rank ordered plurality of C rung switching elements, each coupled between the first plate of a respective one of the capacitors and the common rail, for coupling a respective one of the first plates to the common rail in response to a respective C rung enable signal; a C rail switching network comprising a rank ordered plurality of C rail switching elements, the first of which is coupled between the first reference voltage and the first plate of the capacitor of lowest rank, the last of which is coupled between the second reference voltage and the first plate of the capacitor of highest rank, and the balance of which are coupled between the first plates of respective, successively ordered pairs of the capacitors, for decoupling, in response to a rail disable signal, the first plate of the selected one of the capacitors from the first plates of the capacitors of lower and higher rank; and C ladder logic means coupled to the C rung and C rail switching networks, for providing, in response to the digital input code, said C rung enable signal and said C rail disable signal.

Claim 4

A converter for providing an analog output signal corresponding to a digital input code, comprising: voltage divider means for providing a step voltage selected between first and second reference voltages in response to the digital input code, comprising: resistance means coupled between the first and second reference voltages, for developing on each of a plurality of step nodes a predetermined step voltage between the first and second reference voltages; R ladder switching means coupled between the resistance means and a common rail, for coupling, in response to the digital code, a selected one of the step nodes to the common rail; and charge redistribution means coupled to the common rail, for providing the analog output signal as a function of the step voltage on the common rail and the digital input code, comprising: capacitance means comprising a rank ordered plurality of capacitors having respective first plates and interconnected second plates, for developing the analog output signal on the second plates as a function of the voltages coupled to the first plates; a C rung switching network comprising a rank ordered plurality of C rung switching elements, each coupled between the first plate of a respective one of the capacitors and the common rail, for coupling a respective one of the first plates to the common rail in response to a respective C rung enable signal; a C rail switching network comprising a rank ordered plurality of C rail switching elements, the first of which is coupled between the first reference voltage and the first plate of the capacitor of lowest rank, the last of which is coupled between the second reference voltage and the first plate of the capacitor of highest rank, and the balance of which are coupled between the first plates of respective, successively ordered pairs of the capacitors, for decoupling, in response to a rail disable signal, the first plate of the selected one of the capacitors from the first plates of the capacitors of lower and higher rank; and C ladder logic means coupled to the C rung and C rail switching networks, for providing, in response to the digital input code, said C rung enable signal and said C rail disable signal.

Claim 5

The converter of claim 2 wherein the capacitors comprising the capacitance means are binarily weighted, with the ordering thereof from lowest rank to highest rank being in accordance with said binary weighting.

Claim 6

The converter of claim 2 wherein the C ladder logic means comprise: C decoder means having a rank ordered plurality of C rung outputs coupled to respective ones of the C rung switching elements, for providing the C rung enable signal on a particular one of the C rung outputs in response to each digital input code; and C rail logic means comprising a rank ordered plurality of gates, the first of which has an input coupled to the lowest ranked C rung output and an output coupled to the first C rail switching element, the last of which has an input coupled to the highest ranked C rung output and an output coupled to the last C rail switching element, and the balance of which have inputs coupled to respective adjacent pairs of the C rung outputs, beginning from lowest rank to highest rank, and an output coupled to a respective one of the ranked C rail switching elements, for providing the C rail disable signal to a respective adjacent pair of the C rail switching elements in response to the C rung enable signal on a particular one of the C rung outputs.

Claim 7

The converter of claim 2 wherein the R ladder switching means comprise: an R rung switching network comprising a rank ordered plurality of R rung switching elements, each coupled between a respective one of the step nodes and the common rail; and R logic means coupled to the R rung switching network for providing an R rung enable signal to a particular one of the R rung switching elements in response to the digital input code.

Claim 8

The converter of claim 5 wherein the R logic means comprise: R decoder means comprising a rank ordered plurality of R rung outputs coupled to respective ones of the R rung switching elements, for providing the R rung enable signal on a particular one of the R rung outputs in response to each digital input code.

Claim 9

The converter of claim 6 wherein the first and last C rail switching elements are responsive to a second disable signal, for decoupling the first plates of the capacitance means from both the first and second reference voltages, and responsive to a third disable signal, for decoupling the first plates of the capacitance means from the first reference voltage and coupling the first plates of the capacitance means to the second reference voltage.

Claim 10

The converter of claim 7 further comprising input switching means, for coupling an analog input voltage to the first plates of the capacitance means in response to the second disable signal.

Claim 11

The converter of claim 4 further comprising a dividing capacitor interposed between the second plates of the capacitors of less than a predetermined rank order and the second plates of the capacitors of at least the predetermined rank order.

Claim 12

The circuit of claim 8 further comprising: positive reference voltage means, for providing a positive reference voltage greater than the second reference voltage; negative reference voltage means, for providing a negative reference less than the second reference voltage; and reference switching means, for providing a particular one of the positive and negative reference voltages as the first reference voltage in response to the digital input code.

Claim 13

The circuit of claim 10 further comprising: a coding capacitor having a first plate, and a second plate coupled to the second plate of the lowest ranked capacitor of the capacitance means; first code switching means for coupling the first plate of the coding capacitor to the first plate of the lowest ranked capacitor of the capacitance means in response to an A-law PCM conversion signal; and second code switching means, for coupling the first plate of the coding capacitor to the second reference voltage in response to a Mu-law PCM conversion signal.

Claim 14

The circuit of claim 11 wherein the resistance means further comprises: a plurality of resistors, the first of which is coupled between the second reference voltage and the step node of lowest rank, the last of which is coupled between the first reference voltage and the step node of highest rank, and the balance of which are coupled between successively ordered pairs of the step nodes.

Claim 15

The circuit of claim 12 wherein the highest ordered resistor has a predetermined value, and each of the other resistors has a value of twice the predetermined value of the highest ordered resistor.

Claim 16

The circuit of claim 13 further comprising: an upshift resistor interposed between the first reference voltage and the highest ordered resistor and having a value equal to the predetermined value; upshift switching means coupled in parallel to the upshift resistor, for shorting the upshift resistor in response to the inverse of a correction signal; a downshift resistor interposed between the second reference voltage and the lowest ordered resistor and having a value equal to the predetermined value; downshift switching means coupled in parallel to the downshift resistor, for shorting the downshift resistor in response to the correction signal; and control means coupled to the upshift and downshift switching means, for selectively providing the correction signal to provide one-half LSB correction.