US4077035A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-stage weighted capacitor circuit for analog-to-digital and digital-to-analog converters
Assignee: International Business Machines Corp
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Filing: 1976-05-10
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Granted: 1978-02-28
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Expires: 1996-05-10
Abstract
Abstract A two-stage weighted capacitor network for use as an analog-to-digital or digital-to-analog converter is described. A capacitor ladder is included having two similar groups of capacitors connected in parallel. In each group the parallel capacitors have values starting with value C and decreasing in binary fractional amounts C/2 1 , C/2 2 , C/2 3 , C/2 4 etc. to C/2 n-1 . The two groups are interconnected through a coupling capacitor of value C/2 n-1 and each of the capacitors in the two groups are selectively connected through switches to either a reference voltage or ground potential. A high gain amplifier connected as an inverting amplifier with a 2C capacitor feedback path is connected to the capacitor ladder. When the circuit is used in a digital-to-analog converter, the 2C capacitor is reset and then the digital input pattern, consisting of 2n bits, is manifested by connecting the capacitor ladder switches to the ground potential for "1" bits and leaving the other switches connected to the reference potential for "0" bits. When the circuit is used in an analog-to-digital converter the output of the amplifier is connected to a comparator which serves as a polarity detector and which feeds a set of control logic. The control logic then sets the switches, which were originally all connected to the analog voltage, in a binary search mode.
Inventors
- 👤 Yen Sung Yee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:46
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/80; H03M1/802
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
241 words
A two-stage weighted capacitor signal conversion circuit comprising a first network of capacitors including a plurality of n/2 capacitors, said capacitors having decreasing fractional values from C/2° to C/2.sup.(n/2-1) where n is an integer, an amplifier means including an input and output lead and a feedback capacitor connected between said input and output leads and wherein one side of each of said capacitors of said first network is connected to said amplifier input lead at a first node, a second network of capacitors including a plurality of n/2 capacitors, said capacitors having decreasing fractional values from C/2° to C/2.sup.(n/2-1), one side of each of said capacitors of said second network being connected together at a second node, a coupling capacitor of value C/2.sup.(n/2-1) connected between said first and second node, a plurality of n switches, each switch connected to the other side of a separate one of said n capacitors of said first and second networks, said switches being adapted to be selectively connected to at least a first reference potential and a second reference potential, wherein said amplifier means functions to maintain said first node constantly fixed at said second reference potential and wherein said plurality of switches are selectively actuated in accordance with a digital signal representation to establish electrical paths through said capacitors connected thereto to provide an analog signal on the otput lead of said amplifier means which is an analog representation of said digital signal representation.
Claim 2
Dependent Claim
241 words
A two-stage weighted capacitor signal conversion circuit comprising a first network of capacitors including a plurality of n/2 capacitors, said capacitors having decreasing fractional values from C/2° to C/2.sup.(n/2-1) where n is an integer, an amplifier means including an input and output lead and a feedback capacitor connected between said input and output leads and wherein one side of each of said capacitors of said first network is connected to said amplifier input lead at a first node, a second network of capacitors including a plurality of n/2 capacitors, said capacitors having decreasing fractional values from C/2° to C/2.sup.(n/2-1), one side of each of said capacitors of said second network being connected together at a second node, a coupling capacitor of value C/2.sup.(n/2-1) connected between said first and second node, a plurality of n switches, each switch connected to the other side of a separate one of said n capacitors of said first and second networks, said switches being adapted to be selectively connected to at least a first reference potential and a second reference potential, wherein said amplifier means functions to maintain said first node constantly fixed at said second reference potential and wherein said plurality of switches are selectively actuated in accordance with a digital signal representation to establish electrical paths through said capacitors connected thereto to provide an analog signal on the otput lead of said amplifier means which is an analog representation of said digital signal representation.
Claim 3
Dependent Claim
27 words
A signal conversion circuit according to claim 1 wherein said amplifier means is an inverting amplifier having a second input lead connected to said second reference potential.
Claim 4
Dependent Claim
26 words
A signal conversion circuit according to claim 1 wherein said feedback capacitor has a value 2C and includes a reset switch connected across the terminals thereof.
Claim 5
Dependent Claim
128 words
A signal conversion circuit according to claim 1 further including a source of input analog signal, a comparator means connected to said source of said input analog signal and the output lead of said amplifier means and responsive to said analog signal therefrom for comparing said two analog signals and for producing a comparison signal, storage means connected to said comparator means for storing said comparison signal, said storage means also connected to said plurality of n switches for selectively operating said switches in accordance with said comparison signal for producing a successive analog signal on said amplifier means output lead until the output from said comparator means is zero and said plurality of n switches are set in a digital sequence representative of said input analog signal.
Claim 6
Dependent Claim
41 words
A signal conversion circuit according to claim 4 wherein said storage means includes a storage register, a sequencing means connected to said storage register for controlling the operation of said register, and a clock signal means connected to said sequencing means.
Claim 7
Dependent Claim
164 words
A signal conversion circuit according to claim 1 further including a source of input analog signal and wherein said plurality of n switches are adapted to be selectively connected to said first reference potential, said second reference potential and to said input analog signal, a polarity detector means connected to said second reference potential and the output lead of said amplifier means and responsive to said analog signal therefrom for detecting the polarity of said analog signals and for producing an output signal based on said polarity, storage means connected to said polarity detector means for storing said detector output signal, said storage means also connected to said plurality of n switches for selectively operating said switches in accordance with said polarity detector output signal for producing a successive analog signal on said amplifier means output lead until the output of said amplifer means is zero and said plurality of n switches are set in a digital sequence representative of said input analog signal.
Claim 8
Dependent Claim
41 words
A signal conversion circuit according to claim 6 wherein said storage means includes a storage register, a sequencing means connected to said storage register for controlling the operation of said register, and a clock signal means connected to said sequencing means.
References Cited (Backward Citations)
US2889549A
Cited
US3810158A
Cited
US3594782A
Cited
US3611356A
Cited
US3651518A
Cited
US3653030A
Cited
US3665458A
Cited
US3836906A
Cited
US3999123A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-27 | 1981-08-29 | 1982-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-27 | 1985-08-29 | 1986-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-27 | 1989-08-29 | 1990-02-28 | $7700.00 | Window Closed / Lapsed |