US3665458A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Capacitor ladder network
Assignee: Boeing Co
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Filing: 1970-05-14
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Granted: 1972-05-23
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Expires: 1990-05-14
Abstract
Abstract A high speed digital to analog converter which utilizes capacitors. A capacitor ladder network in combination with switching means for selectively excluding individual ones of the capacitors from the network depending upon the parallel binary input signal information present is determinative of the analog output signal of the converter.
Inventors
- 👤 Owen R Mulkey
- 👤 Charles A Kleingartner
- 👤 Arnold A Zoutte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:36
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/78
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
156 words
A digital to analog converter comprising: a first predetermined reference potential; a second predetermined reference potential unequal to said first predetermined reference potential; a plurality of first capacitors having equal capacitance values; a plurality of second capacitors having equal capacitance values; N conductive members, the first and Nth one of said N conductive members each coupled through one of said first capacitors to said first predetermined reference potential; said first conductive member also providing the output terminal of said analog converter; one of said second capacitors coupled in series between each consecutive pair of said N conductive members; N switching means operable in response respectively to each of N information bits of a binary input signal for controlling the insertion respectively of individual ones of said first capacitors between respective ones of said N conductive members and said first reference potential or said second reference potential depending upon the information content of said binary input signal.
Claim 2
Dependent Claim
156 words
A digital to analog converter comprising: a first predetermined reference potential; a second predetermined reference potential unequal to said first predetermined reference potential; a plurality of first capacitors having equal capacitance values; a plurality of second capacitors having equal capacitance values; N conductive members, the first and Nth one of said N conductive members each coupled through one of said first capacitors to said first predetermined reference potential; said first conductive member also providing the output terminal of said analog converter; one of said second capacitors coupled in series between each consecutive pair of said N conductive members; N switching means operable in response respectively to each of N information bits of a binary input signal for controlling the insertion respectively of individual ones of said first capacitors between respective ones of said N conductive members and said first reference potential or said second reference potential depending upon the information content of said binary input signal.
Claim 3
Dependent Claim
17 words
A digital to analog converter according to claim 1 wherein said first reference potential comprises ground potential.
Claim 4
Dependent Claim
25 words
A digital to analog converter according to claim 1 wherein said second capacitors have capacitance values greater than the capacitance values of said first capacitors.
Claim 5
Dependent Claim
33 words
A digital to analog converter according to claim 3 wherein the capacitance values of each of said second capacitors is equal to about twice the capacitance values of each of said first capacitors.
Claim 6
Dependent Claim
33 words
A digital to analog converter according to claim 4 wherein the capacitances of said second capacitors are equal to 2000 picofarads and the capacitances of said first capacitors are equal to 1000 picofarads.
Claim 7
Dependent Claim
108 words
A digital information signal processing circuit comprising: N input terminals for receiving N control signals; an output terminal; a plurality of first capacitors having equal capacitance values; a plurality of second capacitors having equal cApacitance values greater than the capacitance values of said first capacitors; means for coupling said second capacitors in series between said output terminal and ground potential; N switching means responsive to said N control signals applied to said N input terminals for controlling the insertion of N of said first capacitors in circuit between said series coupled second capacitors and reference potential or ground potential depending upon the information content of said control signals.
Claim 8
Dependent Claim
108 words
A digital information signal processing circuit comprising: N input terminals for receiving N control signals; an output terminal; a plurality of first capacitors having equal capacitance values; a plurality of second capacitors having equal cApacitance values greater than the capacitance values of said first capacitors; means for coupling said second capacitors in series between said output terminal and ground potential; N switching means responsive to said N control signals applied to said N input terminals for controlling the insertion of N of said first capacitors in circuit between said series coupled second capacitors and reference potential or ground potential depending upon the information content of said control signals.
Claim 9
Dependent Claim
29 words
A digital information signal processing circuit in accordance with claim 6 wherein said second capacitors have a capacitance value equal to twice the capacitance values of said first capacitors.
Claim 10
Dependent Claim
69 words
A digital to analog signal converter comprising: a ladder network of symmetrical T-section networks; each of said T-section networks having a first capacitor forming the base of said T-section network and second capacitors forming the arms of said T-section network; switching means responsive to a control signal for selectively coupling said first capacitor to ground or to a reference potential depending upon the amplitude level of said control signal.
Claim 11
Dependent Claim
69 words
A digital to analog signal converter comprising: a ladder network of symmetrical T-section networks; each of said T-section networks having a first capacitor forming the base of said T-section network and second capacitors forming the arms of said T-section network; switching means responsive to a control signal for selectively coupling said first capacitor to ground or to a reference potential depending upon the amplitude level of said control signal.
Claim 12
Dependent Claim
21 words
A digital to analog converter according to claim 8 wherein said first capacitor has a capacitance value of about 1000 picofarads.
Claim 13
Dependent Claim
34 words
A digital to analog converter according to claim 8 wherein said switching means is arranged to couple said first capacitor to reference potential when said control signal level is representative of a logical ONE.
Claim 14
Dependent Claim
75 words
A digital to analog signal converter comprising: an output terminal; a plurality of capacitors having equal capacitance values; means for coupling said capacitors in series circuit between said output terminal and ground; a plurality of further capacitors having equal capacitance values; a plurality of switching means responsive to binary input signals having high and low voltage levels for selectively completing circuits including said further capacitors between said series circuit and ground or a reference potential.
Claim 15
Dependent Claim
75 words
A digital to analog signal converter comprising: an output terminal; a plurality of capacitors having equal capacitance values; means for coupling said capacitors in series circuit between said output terminal and ground; a plurality of further capacitors having equal capacitance values; a plurality of switching means responsive to binary input signals having high and low voltage levels for selectively completing circuits including said further capacitors between said series circuit and ground or a reference potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |