Redistribution circuit for analog to digital and digital to analog conversion and multilevel pre-equalizers

Claim 2

In a system which utilizes analog type signals coded as digital type signals comprising binary words, each word being associated with an analog sample and each digit of a word being associated with a quantizing level of the coded sample, apparatus for converting signals of one type to corresponding signals of the other type comprising: a reference voltage source; a source of timing pulses; a plurality of capacitors, each capacitor corresponding to a different digit in the binary words and each being connected on one side to ground; charging means, under the control of the timing pulses, for selectively charging each of said capacitors upon the occurrence of its corresponding digit pulse, the charge placed on each of said capacitors being weighted in accordance with the binary digit with which each capacitor is associated; and, means, under the control of the timing pulses, for connecting said capacitors in parallel to an output bus at a time subsequent to the charging of said capacitors.

Claim 3

Apparatus as described in claim 1 and furtHer including means, under the control of the timing pulses, for comparing the analog sample voltage with the voltage on said output bus and for producing digital signals representative of these comparisons.

Claim 4

Apparatus as described in claim 2 and further including means, responsive to the signal to be converted, for selecting the polarity of said reference voltage source, said reference voltage source being capable of producing a reference voltage of either polarity.

Claim 5

A signal converting means as claimed in claim 1 wherein said charging means comprises a plurality of resistors separated by taps, switching means for connecting said taps and said capacitors, and means, under the control of timing pulses and responsive to digital signal pulses, for operating said switching means.

Claim 6

In a transmission system which utilizes analog type signals transmitted in the form of multilevel digital type signals, means for equalizing the multilevel digital type signals to compensate for distortion introduced by a transmission medium comprising means for encoding the analog type signals as binary words, each word being associated with a sample of the analog signal and each digit of a word being associated with a quantizing level of the coded sample, a source of timing pulses, a plurality of capacitive circuits, each comprising a variable reference voltage source, a plurality of switched capacitors, each being weighted to correspond to a digit in the binary words and each being connected on one side by first switching means between a redistribution bus and a grounding bus and on the other side to said grounding bus, a fixed capacitor connected between said redistribution bus and said grounding bus, a plurality of control shift registers, each being associated with one of said capacitors and responsive to the associated digit of a binary word, the position of said first switching means being controlled by the state of said controlling shift registers, and second switching means, under the control of the timing pulses, for connecting said variable reference voltage source to said grounding bus and to said redistribution bus and for connecting said grounding bus to ground, a plurality of intermediary shift registers, each being connected between corresponding controlling shift registers of said capacitive circuits, and means, under the control of the timing pulses, for connecting all of said capacitors in parallel to an output bus.

Claim 7

In a transmission system which utilizes analog type signals transmitted in the form of multilevel digital type signals, means for equalizing the multilevel digital type signals to compensate for distortion introduced by a transmission medium comprising means for encoding the analog type signals as binary words, each word being associated with a sample of the analog signal and each digit of a word being associated with a quantizing level of the coded sample, a source of timing pulses, a plurality of capacitive circuits, each comprising a variable reference voltage source, a plurality of switched capacitors, each being weighted to correspond to a digit in the binary words and each being connected on one side by first switching means between a redistribution bus and a grounding bus and on the other side to said grounding bus, a fixed capacitor connected between said redistribution bus and said grounding bus, a plurality of control shift registers, each being associated with one of said capacitors and responsive to the associated digit of a binary word, the position of said first switching means being controlled by the state of said controlling shift registers, and second switching means, under the control of the timing pulses, for connecting said variable reference voltage source to said grounding bus and to said redistribution bus and for connecting said grounding bus to ground, a plurality of intermediary shift registers, each being connected between corresponding controlling shift registers of said capacitive circuits, and means, under the control of the timing pulses, for connecting all of said capacitors in parallel to an output bus.

Claim 8

An encoder for converting analog type signals and digital type signals, one to the other, comprising: a reference voltage source; a plurality of capacitors, each capacitor being associated with a different digit of a digital word; and means, responsive to a first timing signal and to the digits of a digital word, for selectively connecting said voltage source to those capacitors of said plurality of capacitors which will establish a charge on the selected capacitors equivalent to a quantization level corresponding to said digital word, and for subsequently connecting, in response to a second timing signal, all of said plurality of capacitors in parallel, whereby the charge on the selected capacitors redistributes among said plurality of capacitors to establish a voltage equivalent to said quantization level.

Claim 9

An encoder for converting analog type signals and digital type signals, one to the other, comprising: a reference voltage source; a plurality of capacitors, each capacitor being associated with a different digit of a digital word; and means, responsive to a first timing signal and to the digits of a digital word, for selectively connecting said voltage source to those capacitors of said plurality of capacitors which will establish a charge on the selected capacitors equivalent to a quantization level corresponding to said digital word, and for subsequently connecting, in response to a second timing signal, all of said plurality of capacitors in parallel, whereby the charge on the selected capacitors redistributes among said plurality of capacitors to establish a voltage equivalent to said quantization level.

Claim 10

An encoder as described in claim 6 and further including a first capacitor, said first capacitor being connected to said reference voltage source during said first timing signal and being connected to said plurality of capacitors during said second timing signal.