Delay-locked loop with feedback compensation

Claim 3

The method of claim 1 wherein said adjusting said delaying comprises making fine and coarse delay adjustments.

Claim 4

The method of claim 1 wherein said delaying temporarily comprises making fine and coarse delay adjustments.

Claim 5

The method of claim 1 wherein: said delaying delays said reference signal by a first number of clock periods; and said delaying temporarily occurs for a second number of clock periods less than said first number of clock periods.

Claim 8

The method of claim 5 wherein said temporarily adjusting comprises delaying only one of said reference and output signals.

Claim 9

The method of claim 5 wherein said adjusting comprises adjusting the phase of said output signal.

Claim 10

The method of claim 7 wherein said temporarily adjusting comprises adjusting the phase of said output signal by the same amount of phase as said adjusting.

Claim 11

A delay-locked loop circuit comprising: a variable delay having an input operative to receive a periodic reference signal, an output, and a control input, said control input operative to vary the delay of a signal propagating from said variable delay input to said variable delay output; a phase detector having a first input operative to receive said periodic reference signal, a second input, and an output coupled to said variable delay control input, said phase detector operative to detect a phase difference between signals received at its first and second inputs and to vary said delay of said variable delay based on said detected difference; a counter having an input coupled to receive said reference signal and an output, said counter operative to output a signal after counting a number of reference signal clock cycles, said counting commencing substantially upon said phase detector causing said delay of said variable delay to be varied; and a delay unit having an input coupled to said variable delay output, a control input coupled to said counter output, and an output coupled to said phase detector second input, said delay unit operative to delay a signal received at said delay unit input in accordance with a first signal received at said control input and operative to pass a signal received at said delay input substantially without delay in accordance with a second signal received at said control input.

Claim 12

A delay-locked loop circuit comprising: a variable delay having an input operative to receive a periodic reference signal, an output, and a control input, said control input operative to vary the delay of a signal propagating from said variable delay input to said variable delay output; a phase detector having a first input operative to receive said periodic reference signal, a second input, and an output coupled to said variable delay control input, said phase detector operative to detect a phase difference between signals received at its first and second inputs and to vary said delay of said variable delay based on said detected difference; a counter having an input coupled to receive said reference signal and an output, said counter operative to output a signal after counting a number of reference signal clock cycles, said counting commencing substantially upon said phase detector causing said delay of said variable delay to be varied; and a delay unit having an input coupled to said variable delay output, a control input coupled to said counter output, and an output coupled to said phase detector second input, said delay unit operative to delay a signal received at said delay unit input in accordance with a first signal received at said control input and operative to pass a signal received at said delay input substantially without delay in accordance with a second signal received at said control input.

Claim 13

The circuit of claim 9 further comprising a second delay unit having an input operative to receive said reference signal, a control input coupled to said counter output, and an output coupled to said phase detector first input, said delay unit operative to delay a signal received at said delay unit input in accordance with a first signal received at said control input and operative to pass a signal received at said delay input substantially without delay in accordance with a second signal received at said control input.

Claim 14

A delay-locked loop circuit comprising: a first variable delay line having an input operative to receive a periodic reference signal, an output, and a control input, said control input operative to vary the delay of a signal propagating from said first variable delay input to said first variable delay output line; a second variable delay line having an input operative to receive said first variable delay output, an output, and a control input, said control input operative to vary the delay of a signal propagating from said second variable delay input to said second variable delay output line; a phase detector having a first input operative to receive said periodic reference signal, a second input, and first and second variable delay line control outputs, said detector operative to detect a phase difference between signals received at its first and second inputs and to vary said delay of at least one of said first and second variable delay lines based on said detected difference; a counter having an input coupled to receive said periodic reference signal and an output, said counter operative to output a signal after counting a number of clock cycles of said reference signal; a delay unit having an input coupled to said second variable delay output and an output coupled to said phase detector second input, said delay unit operative to delay a signal propagating between said delay unit input and said delay unit output, wherein said delay is varied in response to said phase detector varying said delay of at least one of said first and second variable delay lines until said number of clock cycles has been counted.

Claim 15

A delay-locked loop circuit comprising: a first variable delay line having an input operative to receive a periodic reference signal, an output, and a control input, said control input operative to vary the delay of a signal propagating from said first variable delay input to said first variable delay output line; a second variable delay line having an input operative to receive said first variable delay output, an output, and a control input, said control input operative to vary the delay of a signal propagating from said second variable delay input to said second variable delay output line; a phase detector having a first input operative to receive said periodic reference signal, a second input, and first and second variable delay line control outputs, said detector operative to detect a phase difference between signals received at its first and second inputs and to vary said delay of at least one of said first and second variable delay lines based on said detected difference; a counter having an input coupled to receive said periodic reference signal and an output, said counter operative to output a signal after counting a number of clock cycles of said reference signal; a delay unit having an input coupled to said second variable delay output and an output coupled to said phase detector second input, said delay unit operative to delay a signal propagating between said delay unit input and said delay unit output, wherein said delay is varied in response to said phase detector varying said delay of at least one of said first and second variable delay lines until said number of clock cycles has been counted.

Claim 16

The circuit of claim 11 further comprising a second delay unit having an input operative to receive said reference signal and an output coupled to said phase detector first input, said delay unit operative to delay a signal propagating between said delay unit input and said delay unit output, wherein said delay is varied in response to said phase detector varying said delay of one of said first and second variable delay lines until said number of clock cycles has been counted.

Claim 17

The circuit of claim 11 wherein said first variable delay is operative to provide coarse delay adjustments.

Claim 18

The circuit of claim 11 wherein said second variable delay is operative to provide fine delay adjustments.

Claim 19

The circuit of claim 11 wherein said counter is operative to commence counting substantially upon said phase detector causing said delay of said variable delay line to be varied.

Claim 20

Apparatus for adjusting the phase difference between a periodic reference signal and an output signal, said apparatus comprising: means for receiving a periodic reference signal; means for delaying said reference signal to produce an output signal; means for feeding back said output signal; means for measuring a phase difference between said fed back output signal and said reference signal; means for adjusting said means for delaying said reference signal in accordance with said measured phase difference to produce an adjusted output signal; and means for delaying temporarily said reference signal or said fed back signal until said adjusted output signal is fed back; wherein: said means for measuring measures the phase difference between said temporarily delayed reference or fed back signal and the other of said reference and fed back signal until said adjusted output signal is fed back; and said means for adjusting adjusts said delaying of said reference signal in accordance with said measured phase difference between said temporarily delayed signal and the other of said signals reference and fed back to produce a further adjusted output signal.

Claim 21

Apparatus for adjusting the phase difference between a periodic reference signal and an output signal, said apparatus comprising: means for receiving a periodic reference signal; means for delaying said reference signal to produce an output signal; means for feeding back said output signal; means for measuring a phase difference between said fed back output signal and said reference signal; means for adjusting said means for delaying said reference signal in accordance with said measured phase difference to produce an adjusted output signal; and means for delaying temporarily said reference signal or said fed back signal until said adjusted output signal is fed back; wherein: said means for measuring measures the phase difference between said temporarily delayed reference or fed back signal and the other of said reference and fed back signal until said adjusted output signal is fed back; and said means for adjusting adjusts said delaying of said reference signal in accordance with said measured phase difference between said temporarily delayed signal and the other of said signals reference and fed back to produce a further adjusted output signal.

Claim 22

The apparatus of claim 16 wherein said means for adjusting comprises a fine delay adjustment and a coarse delay adjustment.

Claim 23

The apparatus of claim 16 wherein said means for delaying temporarily comprises a fine delay adjustment and a coarse delay adjustment.

Claim 24

The apparatus of claim 16 wherein: said means for delaying delays said reference signal by a first number of clock periods; and said means for delaying temporarily does so for a second number of clock periods less than said first number of clock periods.

Claim 25

Apparatus for adjusting a phase difference between a reference signal and an output signal, said apparatus comprising: means for receiving a reference signal; means for generating an output signal synchronized to said reference signal; means for measuring the phase difference between said reference signal and said output signal; means for adjusting said means for generating an output signal to generate an adjusted output signal in accordance with said measured phase difference; and means for temporarily adjusting at least one of said reference signal and said output signal for use in said means for measuring until said means for measuring can measure the phase difference between said adjusted output signal and said reference signal.

Claim 26

Apparatus for adjusting a phase difference between a reference signal and an output signal, said apparatus comprising: means for receiving a reference signal; means for generating an output signal synchronized to said reference signal; means for measuring the phase difference between said reference signal and said output signal; means for adjusting said means for generating an output signal to generate an adjusted output signal in accordance with said measured phase difference; and means for temporarily adjusting at least one of said reference signal and said output signal for use in said means for measuring until said means for measuring can measure the phase difference between said adjusted output signal and said reference signal.

Claim 27

The apparatus of claim 20 wherein said means for temporarily adjusting comprises means for temporarily adjusting the phase one of said reference and output signals.

Claim 28

The apparatus of claim 20 wherein said means for adjusting comprises means for adjusting the phase of said output signal.

Claim 29

The apparatus of claim 22 wherein said means for temporarily adjusting comprises means for temporarily adjusting the phase of said output signal by the same amount of phase as said means for adjusting.

Claim 30

A computer system comprising: a processor; a memory controller coupled to said processor; and a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising a clock synchronization circuit comprising: a variable delay having an input operative to receive a periodic reference signal, an output, and a control input, said control input operative to vary the delay of a signal propagating from said variable delay input to said variable delay output; a phase detector having a first input operative to receive said reference signal, a second input, and an output, said detector operative to detect a phase difference between signals received at its first and second inputs and to vary said delay of said variable delay based on said detected difference; a counter having an input coupled to receive said reference signal and an output, said counter operative to output a signal after counting a number of clock cycles of said reference signal; and a delay unit having an input coupled to said variable delay output, a control input, and an output coupled to said phase detector second input, said delay unit operative to delay a signal received at said delay unit input in accordance with a first signal received at said control input and operative to pass a signal received at said delay input substantially without delay in accordance with a second signal received at said control input.

Claim 31

A computer system comprising: a processor; a memory controller coupled to said processor; and a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising a clock synchronization circuit comprising: a variable delay having an input operative to receive a periodic reference signal, an output, and a control input, said control input operative to vary the delay of a signal propagating from said variable delay input to said variable delay output; a phase detector having a first input operative to receive said reference signal, a second input, and an output, said detector operative to detect a phase difference between signals received at its first and second inputs and to vary said delay of said variable delay based on said detected difference; a counter having an input coupled to receive said reference signal and an output, said counter operative to output a signal after counting a number of clock cycles of said reference signal; and a delay unit having an input coupled to said variable delay output, a control input, and an output coupled to said phase detector second input, said delay unit operative to delay a signal received at said delay unit input in accordance with a first signal received at said control input and operative to pass a signal received at said delay input substantially without delay in accordance with a second signal received at said control input.