Semiconductor device capable of generating highly precise internal clock

Claim 2

A semiconductor device comprising: an internal clock generation circuit generating an operating clock signal in response to an external clock signal, said internal clock generation circuit including a phase comparator comparing a phase of said external clock signal and that of said operating clock signal with each other, and a clock delay portion responsive to an output of said phase comparator for delaying a first internal clock signal to output said operating clock signal, said clock delay portion having a clock conversion portion generating from said first internal clock a second internal signal and a third internal signal complementary to said second internal signal, and a clock output portion responsive to the output of said phase comparator for changing by one stage a number of gate stages to be passed through, said clock output portion outputting said operating clock in response to said second internal clock signal when said number of gate stages is an odd number of stages, said clock output portion outputting said operating clock signal in response to said third internal clock signal when said number of gate stages is an even number of stages; and an internal circuit operating in response to said operating clock signal.

Claim 3

The semiconductor device according to claim 1 , wherein: said clock delay portion receives said external clock signal as said first internal clock signal; and said internal clock generation circuit is a delay-locked loop (DLL) circuit.

Claim 4

The semiconductor device according to claim 1 , wherein: said clock delay portion receives said operating clock signal as said first internal clock signal and oscillates; and said internal clock generation circuit is a phase-locked loop (PLL) circuit.

Claim 5

The semiconductor device according to claim 1 , wherein: said clock output portion has a plurality of NAND circuits connected in series and corresponding to at least a part of said gate stages, each having a first input node receiving the output of the preceding gate stage and a second input node receiving a fourth internal clock signal corresponding to either one of said second and third internal clock signals, and a selector circuit selecting one of said plurality of NAND circuits and applying said fourth internal clock signal to said second input node of the selected NAND circuit, said selector circuit applying said second internal clock signal as said fourth internal clock signal when said fourth internal clock signal passes through an odd number of stage(s) of said gate stages, said selector circuit applying said third internal clock signal as said fourth internal clock signal when said fourth internal clock signal passes through an even number of stage(s) of said gate stages.

Claim 6

A semiconductor device comprising: an internal clock generation circuit generating an operating clock signal in response to an external clock signal, said internal clock generation circuit including a phase comparator comparing a phase of said external clock signal and a phase of said operating clock signal with each other, and a clock delay portion allowing a delay time to have an initial value set in response to a reset signal, changing said delay time in response to an output of said phase comparator and delaying a first internal clock signal for said delay time to output said operating clock signal, said clock delay portion having a setting switching portion switching said initial value between a first value and a second value increasing said delay time, as compared to said first value, and a clock output portion receiving said initial value from said setting switch portion, changing said delay time in response to the output of said phase comparator and outputting said operating clock signal corresponding to said first internal clock signal delayed; and an internal circuit operating in response to said operating clock signal; wherein: said clock delay portion receives said operating clock signal as said first internal clock signal and oscillates; and said internal clock generation circuit is a phase-locked loop (PLL) circuit.

Claim 7

A semiconductor device comprising: an internal clock generation circuit generating an operating clock signal in response to an external clock signal, said internal clock generation circuit including a phase comparator comparing a phase of said external clock signal and a phase of said operating clock signal with each other, and a clock delay portion allowing a delay time to have an initial value set in response to a reset signal, changing said delay time in response to an output of said phase comparator and delaying a first internal clock signal for said delay time to output said operating clock signal, said clock delay portion having a setting switching portion switching said initial value between a first value and a second value increasing said delay time, as compared to said first value, and a clock output portion receiving said initial value from said setting switch portion, changing said delay time in response to the output of said phase comparator and outputting said operating clock signal corresponding to said first internal clock signal delayed; and an internal circuit operating in response to said operating clock signal; wherein: said clock delay portion receives said operating clock signal as said first internal clock signal and oscillates; and said internal clock generation circuit is a phase-locked loop (PLL) circuit.

Claim 8

A semiconductor device comprising: an internal clock generation circuit generating an operating clock signal in response to an external clock signal, said internal clock generation circuit including a phase comparator comparing a phase of said external clock signal and a phase of said operating clock signal with each other, a first clock delay portion delaying a first internal clock signal for a first delay time determined by an output of said phase comparator, a second clock delay portion delaying an output of said first clock delay portion for a second delay time determined by the output of said phase comparator in a coarser step than said first delay time to output said operating clock, and a control portion instructing said second clock delay portion to fix said second delay time regardless of an output of said phase comparator once said operating clock has achieved a stable state; and an internal circuit operating in response to said operating clock signal.

Claim 9

A semiconductor device comprising: an internal clock generation circuit generating an operating clock signal in response to an external clock signal, said internal clock generation circuit including a phase comparator comparing a phase of said external clock signal and a phase of said operating clock signal with each other, a first clock delay portion delaying a first internal clock signal for a first delay time determined by an output of said phase comparator, a second clock delay portion delaying an output of said first clock delay portion for a second delay time determined by the output of said phase comparator in a coarser step than said first delay time to output said operating clock, and a control portion instructing said second clock delay portion to fix said second delay time regardless of an output of said phase comparator once said operating clock has achieved a stable state; and an internal circuit operating in response to said operating clock signal.

Claim 10

The semiconductor device according to claim 6 , wherein said control portion has a latch circuit outputting to said second clock delay portion a control signal corresponding to control data set once said latch circuit has received from said phase comparator a lock signal indicating that said external clock signal and said internal clock signal have therebetween a phase difference-of no more than a predetermined value.

Claim 11

The semiconductor device according to claim 6 , wherein said control portion has: a counter detecting said external clock signal being input by a predetermined clock count, as counted since power-on; and a latch circuit set in response to an output of said counter to output a control signal for said second clock delay portion.

Claim 12

The semiconductor device according to claim 6 ; wherein: said clock drive portion receives said external clock signal as said first internal clock signal; and said internal clock/generation circuit is a delay-locked loop (DLL) circuit.

Claim 13

The semiconductor device according to claim 6 , wherein: said clock delay portion receives said operating clock signal as said first internal clock signal and oscillates; and said internal clock generation circuit is a phase-locked loop (PLL) circuit.