US6538956B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device for providing address access time and data access time at a high speed
Assignee: SK Hynix Inc
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Filing: 2001-05-30
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Granted: 2003-03-25
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Expires: 2021-05-30
Abstract
Abstract A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.
Inventors
- 👤 Je-Hun Ryu
- 👤 Jong-Hee Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:30
CPC Classifications
G; G11; G11C; G11C8/00; G11C7/00; G11C7/22; G11C7/222; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4087; G11C8/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
164 words
A semiconductor memory device comprising: a clock buffering and generating unit for buffering an external clock and generating an internal clock; a delay locked loop (DLL) for generating a DLL clock in substantial synchronization with the external clock, the DLL including: a clock control unit for receiving a DLL signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal to generate a DLL control signal and a clock selection signal; and a DLL clock buffer unit for generating the DLL clock using the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in substantial synchronization with the DLL clock in response to the DLL control signal; and an address or column address strobe (CAS) buffer for receiving and buffering an external address or CAS signal to generate an internal address or CAS signal in substantial synchronization with the DLL clock in response to the DLL control signal.
Claim 2
Dependent Claim
164 words
A semiconductor memory device comprising: a clock buffering and generating unit for buffering an external clock and generating an internal clock; a delay locked loop (DLL) for generating a DLL clock in substantial synchronization with the external clock, the DLL including: a clock control unit for receiving a DLL signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal to generate a DLL control signal and a clock selection signal; and a DLL clock buffer unit for generating the DLL clock using the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in substantial synchronization with the DLL clock in response to the DLL control signal; and an address or column address strobe (CAS) buffer for receiving and buffering an external address or CAS signal to generate an internal address or CAS signal in substantial synchronization with the DLL clock in response to the DLL control signal.
Claim 3
Dependent Claim
23 words
The semiconductor memory device of claim 1 further comprising a command decoder for decoding the internal control signal to generate a command signal.
Claim 4
Dependent Claim
21 words
The semiconductor memory device of claim 1 , wherein an access time of the semiconductor memory device is below 1.5 nanoseconds.
Claim 5
Dependent Claim
35 words
The semiconductor memory device of claim 1 , wherein the DLL further includes a clock driving unit for receiving the internal clock, the DLL clock and the clock selection signal to generate a third clock.
Claim 6
Independent Claim
81 words
A method of propagating a signal through a semiconductor memory device, comprising the steps of: providing an external clock; buffering the external clock; generating a delay locked loop (DLL) clock in substantial synchronization with the external clock; generating a DLL control signal and a clock selection signal by receiving a DLL signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal; and providing the DLL clock to a control signal buffer and an address buffer.
Claim 7
Independent Claim
81 words
A method of propagating a signal through a semiconductor memory device, comprising the steps of: providing an external clock; buffering the external clock; generating a delay locked loop (DLL) clock in substantial synchronization with the external clock; generating a DLL control signal and a clock selection signal by receiving a DLL signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal; and providing the DLL clock to a control signal buffer and an address buffer.
Claim 8
Dependent Claim
18 words
The method of claim 5 further comprising the step of providing the DLL clock to a CAS buffer.
Claim 9
Dependent Claim
29 words
The method of claim 5 further comprising the step of generating an internal control signal in substantial synchronization with the DLL clock in response to the DLL control signal.
Claim 10
Dependent Claim
38 words
The method of claim 7 , wherein the step of generating the internal control signal is performed by the control signal buffer in response to receiving the DLL clock, an external control signal and the DLL control signal.
Claim 11
Dependent Claim
29 words
The method of claim 5 further comprising the step of generating an internal address signal in substantial synchronization with the DLL clock in response to the DLL control signal.
Claim 12
Dependent Claim
19 words
The method of claim 9 , wherein the step of generating the internal address signal and DLL control signal.
Claim 13
Dependent Claim
27 words
The method of claim 8 further comprising the steps of: decoding the internal control signal; and generating a command signal in response to the step of decoding.
Claim 14
Dependent Claim
20 words
The method of claim 5 , wherein the semiconductor memory device has an access time of less than 1.5 nanoseconds.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-24 | 2006-09-23 | 2007-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-24 | 2010-09-23 | 2011-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-24 | 2014-09-23 | 2015-03-25 | $7700.00 | Window Closed / Lapsed |