US5930177A
Expired / Lapsed
US
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Buffer control circuit and method for semiconductor memory device with power saving function
Assignee: SK Hynix Inc
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Filing: 1997-12-29
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Granted: 1999-07-27
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Expires: 2017-12-29
Abstract
Abstract A buffer control circuit and method for a semiconductor memory device with a power saving function power saving function. The buffer control circuit includes an internal clock signal generator for generating an internal clock signal in response to an external clock signal, an internal chip select signal generator for generating an internal chip select signal in response to an external chip select signal, a buffer control signal generator for combining the internal clock signal from the internal clock signal generator and the internal chip select signal from the internal chip select signal generator to generate a buffer control signal, a command/address buffering circuit operative in response to the buffer control signal from the buffer control signal generator, for storing external input command and address, and a decoder for decoding commands from the command/address buffering circuit. According to the present invention, the amount of current being consumed at a standby state of the semiconductor memory device can be reduced.
Inventors
- 👤 Yong Ki Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/10; G11C7/1072; H; H10; H10D; H10D84/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
147 words
A buffer control circuit for a semiconductor memory device with a power saving function, comprising: internal clock signal generation means for generating an internal clock signal in response to an external clock signal; internal chip select signal generation means for generating an internal chip select signal in response to an external chip select signal; buffer control signal generation means for combining said internal clock signal from said internal clock signal generation means and said internal chip select signal from said internal chip select signal generation means to generate a buffer control signal; command/address buffering means operative in response to said buffer control signal from said buffer control signal generation means, for storing external input command and address; and decoding means for decoding commands from said command/address buffering means; whereby the amount of current being consumed at a standby state of said semiconductor memory device can be reduced.
Claim 2
Dependent Claim
147 words
A buffer control circuit for a semiconductor memory device with a power saving function, comprising: internal clock signal generation means for generating an internal clock signal in response to an external clock signal; internal chip select signal generation means for generating an internal chip select signal in response to an external chip select signal; buffer control signal generation means for combining said internal clock signal from said internal clock signal generation means and said internal chip select signal from said internal chip select signal generation means to generate a buffer control signal; command/address buffering means operative in response to said buffer control signal from said buffer control signal generation means, for storing external input command and address; and decoding means for decoding commands from said command/address buffering means; whereby the amount of current being consumed at a standby state of said semiconductor memory device can be reduced.
Claim 3
Dependent Claim
88 words
The buffer control circuit for a semiconductor memory device with a power saving function, as set forth in claim 1, wherein said internal clock signal generation means includes: a first inverter for inverting said external clock signal; a plurality of second inverters for delaying and inverting an output signal from said first inverter; and a NAND gate for NANDing the output signal from said first inverter and an output signal from the last one of said second inverters and outputting the NANDed result as said internal clock signal.
Claim 4
Dependent Claim
112 words
The buffer control circuit for a semiconductor memory device with a power saving function, as set forth in claim 1, wherein said internal chip select signal generation means includes: an inverter for inverting said external chip select signal and outputting the inverted signal as said internal chip select signal; and a NAND gate for NANDing said internal chip select signal from said inverter and said internal clock signal from said internal clock signal generation means and outputting the NANDed result as a control signal to said decoding means, said control signal from said NAND gate determining the type of said external input command when said external chip select signal is made active.
Claim 5
Dependent Claim
120 words
The buffer control circuit for a semiconductor memory device with a power saving function, as set forth in claim 1, wherein said buffer control signal generation means includes: an inverter for inverting said internal chip select signal from said internal chip select signal generation means; a first NAND gate for NANDing an output signal from said inverter and said internal clock signal from said internal clock signal generation means; a second NAND gate for NANDing an output signal from said first NAND gate and said buffer control signal; and a third NAND gate for NANDing the output signal from said inverter and an output signal from said second NAND gate and outputting the NANDed result as said buffer control signal.
Claim 6
Dependent Claim
59 words
The buffer control circuit for a semiconductor memory device with a power saving function, as set forth in claim 1, wherein said buffer control signal from said buffer control signal generation means is made active when a clock enable signal is enabled and said external chip select signal is disabled, to control an operation of said command/address buffering means.
Claim 7
Dependent Claim
122 words
The buffer control circuit for a semiconductor memory device with a power saving function, as set forth in claim 1, wherein said command/address buffering means includes: a buffer for storing said external input command; a switching element being turned on/off in response to said buffer control signal from said buffer control signal generation means to control an operation of said buffer; and a NAND gate for NANDing an output signal from said buffer and said internal clock signal from said internal clock signal generation means and outputting the NANDed result as a control signal to said decoding means, said control signal from said NAND gate determining the type of said external input command when said external chip select signal is made active.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |