US6445231B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital dual-loop DLL design using coarse and fine loops
Assignee: Round Rock Research LLC
•
Filing: 2000-06-01
•
Granted: 2002-09-03
•
Expires: 2020-06-01
Abstract
Abstract A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.
Inventors
- 👤 R. Jacob Baker
- 👤 Feng Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:08
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
125 words
A delay locked loop system comprising: a coarse loop to produce a first delayed signal, the coarse loop including a delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; and a fine loop connected to the coarse loop to receive the first delay signal to produce a second delayed signal, the fine loop having a delay range, wherein the delay range of the fine loop is substantially smaller than the delay range of the coarse loop.
Claim 2
Dependent Claim
125 words
A delay locked loop system comprising: a coarse loop to produce a first delayed signal, the coarse loop including a delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; and a fine loop connected to the coarse loop to receive the first delay signal to produce a second delayed signal, the fine loop having a delay range, wherein the delay range of the fine loop is substantially smaller than the delay range of the coarse loop.
Claim 3
Dependent Claim
55 words
The delay locked loop of claim 1 , wherein the coarse loop comprises: a first phase detector connected to an input node; a first shift register connected to the phase detector; and a first delay line connected to the input node and the first shift register, the first delay line having a first output node.
Claim 4
Dependent Claim
58 words
The delay locked loop system of claim 1 , wherein the fine loop comprises: a fine phase detector connected to the input node; a fine shift register connected to the fine phase detector; and a fine delay line connected to the fine shift register, the fine delay line having an output node to produce the second delayed signal.
Claim 5
Dependent Claim
31 words
The delay locked loop system of claim 1 , wherein the coarse loop further comprises a plurality of delay stages, when one delay stage is activated, previous delay stages are disabled.
Claim 6
Dependent Claim
47 words
The delay locked loop of claim 4 , wherein each of the delay stages comprises a plurality of delay cells, each of the delay cells having a plurality of delay elements, wherein the delay elements are the same type of elements and have the same time delay.
Claim 7
Dependent Claim
49 words
The delay locked loop of claim 2 , wherein the first delay line has an entry point, wherein the entry point is shifted by the first shift register in one direction to increase the amount of delay and is shifted in another direction to decrease the amount of delay.
Claim 8
Dependent Claim
35 words
The delay locked loop system of claim 3 further comprising a delay model circuit connected to the coarse and fine loops, the delay model circuit delaying the second delayed signal to provide a feedback signal.
Claim 9
Dependent Claim
177 words
A delay locked loop system comprising: a first input node to receive an input signal; a second input node to receive a feedback signal; a coarse loop connected to the first and second input nodes to receive the input and feedback signals to produce a first delayed signal, wherein the first delay and feedback signals have a skew, the coarse loop including: a phase detector connected to the first and second input nodes; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; and a fine loop connected to the first and second input nodes and the coarse loop to receive the input, feedback and first delayed signals to produce a second delayed signal, the second delayed and feedback signals having a skew that is smaller than the skew between the first delayed and feedback signal.
Claim 10
Dependent Claim
177 words
A delay locked loop system comprising: a first input node to receive an input signal; a second input node to receive a feedback signal; a coarse loop connected to the first and second input nodes to receive the input and feedback signals to produce a first delayed signal, wherein the first delay and feedback signals have a skew, the coarse loop including: a phase detector connected to the first and second input nodes; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; and a fine loop connected to the first and second input nodes and the coarse loop to receive the input, feedback and first delayed signals to produce a second delayed signal, the second delayed and feedback signals having a skew that is smaller than the skew between the first delayed and feedback signal.
Claim 11
Dependent Claim
55 words
The delay locked loop of claim 8 , wherein the coarse loop comprises: a first phase detector connected to an input node; a first shift register connected to the phase detector; and a first delay line connected to the input node and the first shift register, the first delay line having a first output node.
Claim 12
Dependent Claim
61 words
The delay locked loop system of claim 8 , wherein the fine loop comprises: a fine phase detector connected to the first and second inputs node; a fine shift register connected to the fine phase detector; and a fine delay line connected to the first output node and the fine shift register, the fine delay line having a second output node.
Claim 13
Dependent Claim
31 words
The delay locked loop system of claim 8 , wherein the coarse loop further comprises a plurality of delay stages, when one delay stage is activated, unnecessary delay stages are inactivated.
Claim 14
Dependent Claim
47 words
The delay locked loop of claim 11 , wherein each of the delay stages comprises a plurality of delay cells, each of the delay cells having a plurality of delay elements, wherein the delay elements are the same type of elements and have the same time delay.
Claim 15
Dependent Claim
58 words
The delay locked loop system of claim 8 , wherein the delay line has an entry point, wherein the entry point is shifted by the shift register in one direction to increase an amount of delay applied to the input signal and is shifted in another direction to decrease an amount of delay applied to the input signal.
Claim 16
Dependent Claim
21 words
The delay locked loop system of claim 8 further comprising a delay model circuit connected to the coarse and fine loops.
Claim 17
Dependent Claim
185 words
A delay locked loop system comprising: an input node to receive an input signal; a forward path connected to the input node, the forward path having a first delay locked loop circuit and a second delay locked loop circuit, wherein the first delay locked loop circuit has a first delay range and the second delay locked loop circuit has a second delay range, and wherein the forward path produces a delayed signal, wherein the first delay locked loop circuit including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; and a feedback path connected to the forward path to delay the delayed signal to produce a feedback signal, the feedback signal being fed back to the forward, wherein the forward path applies variable amounts of delay to the input signal until the input signal and the feedback signal are synchronized.
Claim 18
Dependent Claim
185 words
A delay locked loop system comprising: an input node to receive an input signal; a forward path connected to the input node, the forward path having a first delay locked loop circuit and a second delay locked loop circuit, wherein the first delay locked loop circuit has a first delay range and the second delay locked loop circuit has a second delay range, and wherein the forward path produces a delayed signal, wherein the first delay locked loop circuit including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; and a feedback path connected to the forward path to delay the delayed signal to produce a feedback signal, the feedback signal being fed back to the forward, wherein the forward path applies variable amounts of delay to the input signal until the input signal and the feedback signal are synchronized.
Claim 19
Dependent Claim
55 words
The delay locked loop of claim 15 , wherein the first loop comprises: a first phase detector connected to an input node; a first shift register connected to the phase detector; and a first delay line connected to the input node and the first shift register, the first delay line having a first output node.
Claim 20
Dependent Claim
61 words
The delay locked loop system of claim 15 , wherein the second delay locked loop circuit comprises: a fine phase detector connected to the input node; a fine shift register connected to the fine phase detector; and a fine delay line connected to the fine shift register, the fine delay line having an output node to produce the second delayed signal.
Claim 21
Dependent Claim
34 words
The delay locked loop system of claim 15 , wherein the first delay locked loop circuit further comprises a plurality of delay stages, when one delay stage is activated, previous delay stages are disabled.
Claim 22
Dependent Claim
47 words
The delay locked loop of claim 18 , wherein each of the delay stages comprises a plurality of delay cells, each of the delay cells having a plurality of delay elements, wherein the delay elements are the same type of elements and have the same time delay.
Claim 23
Dependent Claim
58 words
The delay locked loop system of claim 15 , wherein the delay line has an entry point, wherein the entry point is shifted by the shift register in one direction to increase an amount of delay applied to the input signal and is shifted in another direction to decrease an amount of delay applied to the input signal.
Claim 24
Dependent Claim
28 words
The delay locked loop system of claim 15 , wherein the feedback path comprising a delay model circuit to delay the delayed signal to provide the feedback signal.
Claim 25
Dependent Claim
176 words
A delay locked loop system comprising: an input node to receive a clock signal; a coarse loop comprising: a phase detector connected to the input node; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the clock signal has a first skew; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal have a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a feedback signal.
Claim 26
Dependent Claim
176 words
A delay locked loop system comprising: an input node to receive a clock signal; a coarse loop comprising: a phase detector connected to the input node; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the clock signal has a first skew; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal have a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a feedback signal.
Claim 27
Dependent Claim
31 words
The delay locked loop system of claim 22 , wherein the coarse loop further comprises a plurality of delay stages, when one delay stage is activated, previous delay stages are disabled.
Claim 28
Dependent Claim
47 words
The delay locked loop of claim 23 , wherein each of the delay stages comprises a plurality of delay cells, each of the delay cells having a plurality of delay elements, wherein the delay elements are the same type of elements and have the same time delay.
Claim 29
Dependent Claim
58 words
The delay locked loop system of claim 22 , wherein the delay line has an entry point, wherein the entry point is shifted by the shift register in one direction to increase an amount of delay applied to the input signal and is shifted in another direction to decrease an amount of delay applied to the input signal.
Claim 30
Dependent Claim
179 words
A memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprises: a coarse loop to produce a first delayed signal, the coarse loop including a first delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to the coarse loop to receive the first delay signal to produce a second delayed signal, the fine loop having a second delay range, wherein the second delay range is substantially smaller than the first delay range; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 31
Dependent Claim
179 words
A memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprises: a coarse loop to produce a first delayed signal, the coarse loop including a first delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to the coarse loop to receive the first delay signal to produce a second delayed signal, the fine loop having a second delay range, wherein the second delay range is substantially smaller than the first delay range; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 32
Dependent Claim
19 words
The memory of claim 26 , wherein the delay model circuit and the output circuit have the same construction.
Claim 33
Dependent Claim
215 words
A memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive an input signal; a coarse loop connected to the input node to receive the input signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew, the coarse loop including: a phase detector connected to the first and second input nodes; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the input signal has a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 34
Dependent Claim
215 words
A memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive an input signal; a coarse loop connected to the input node to receive the input signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew, the coarse loop including: a phase detector connected to the first and second input nodes; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the input signal has a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 35
Dependent Claim
19 words
The memory of claim 28 , wherein the delay model circuit and the output circuit have the same construction.
Claim 36
Dependent Claim
214 words
A memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive a clock signal; a coarse loop comprising: a phase detector connected to the input node; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the clock signal has a first skew; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal have a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a feedback signal.
Claim 37
Dependent Claim
214 words
A memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive a clock signal; a coarse loop comprising: a phase detector connected to the input node; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the clock signal has a first skew; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal have a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a feedback signal.
Claim 38
Dependent Claim
19 words
The memory of claim 30 , wherein the delay model circuit and the output circuit have the same construction.
Claim 39
Independent Claim
186 words
A system comprising: a processor; and a memory device connected to the processor, the memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprises: a coarse loop to produce a first delayed signal, the coarse loop including a first delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to the coarse loop to produce a second delayed signal, the fine loop having a second delay range, wherein the second delay range is substantially smaller than the first delay range; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 40
Independent Claim
186 words
A system comprising: a processor; and a memory device connected to the processor, the memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprises: a coarse loop to produce a first delayed signal, the coarse loop including a first delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to the coarse loop to produce a second delayed signal, the fine loop having a second delay range, wherein the second delay range is substantially smaller than the first delay range; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 41
Independent Claim
224 words
A system comprising: a processor; and a memory device connected to the processor, the memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive an input signal; a coarse loop connected to the input node to receive the input signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew, the coarse loop including: a phase detector connected to the first and second input nodes; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the input signal has a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 42
Independent Claim
224 words
A system comprising: a processor; and a memory device connected to the processor, the memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive an input signal; a coarse loop connected to the input node to receive the input signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew, the coarse loop including: a phase detector connected to the first and second input nodes; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements; a fine loop connected to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the input signal has a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce a strobe signal.
Claim 43
Independent Claim
227 words
A system comprising: a processor; and a memory device connected to the processor, the memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive a clock signal; a coarse loop comprising: a phase detector connected to the input node; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal has a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce an output signal.
Claim 44
Independent Claim
227 words
A system comprising: a processor; and a memory device connected to the processor, the memory device comprising: a main memory; an output circuit connected to the main memory, the output circuit having an output pad for producing an output signal; and a delay locked loop system connected to the output circuit, the delay locked loop system comprising: an input node to receive a clock signal; a coarse loop comprising: a phase detector connected to the input node; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a plurality of delay cells, wherein each of the register cells is connected to two delay cells, wherein each of the delay cells includes a plurality of identical delay elements, wherein the delay cells are connected to the input node to receive the clock signal to produce a first delayed signal, wherein the first delayed signal and the input signal has a first skew; a fine loop connected to the coarse loop to receive the first delayed signal to produce a second delayed signal, wherein the second delayed signal and the clock signal has a second skew, wherein the second skew is substantially smaller than the first skew; and a delay model circuit connected to the fine loop to delay the second delayed signal to produce an output signal.
References Cited (Backward Citations)
US5109394A
Cited
US5355037A
Cited
US5604775A
Cited
US5744991A
Cited
US6130552A
Cited
US6049239A
Cited
US6101197A
Cited
US6297680B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-02 | 2006-03-04 | 2006-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-02 | 2010-03-04 | 2010-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-02 | 2014-03-04 | 2014-09-03 | $7700.00 | Window Closed / Lapsed |