Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution

Claim 2

A programmable logic device comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block; and a multiplexer comprising a first input coupled to the reference clock signal and a second input coupled to the synchronized clock output signal, and the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block through the multiplexer.

Claim 3

The programmable logic device of claim 1 wherein the clock synchronization circuit comprises a delay-locked loop circuit, and the clock synchronization circuit minimizes skew for n clock signals, each of the n clock signals being received at one of n logic blocks.

Claim 4

The programmable logic device of claim 1 wherein the clock synchronization circuit comprises: a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; and a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit.

Claim 5

The programmable logic device of claim 3 wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 6

The programmable logic device of claim 4 wherein the output of the current pump is coupled through a low pass filter to the variable delay circuit.

Claim 7

The programmable logic device of claim 3 wherein the control circuit comprises: a delay element, coupled between the synchronized clock output signal and the feedback clock signal.

Claim 8

The programmable logic device of claim 3 wherein the control circuit comprises: a macro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the macro phase detect circuit generates a first signal indicating a first phase difference between the reference clock signal and the feedback clock signal of at least a threshold amount; and a micro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the micro phase detect circuit generates a second signal indicating a second phase difference between the reference clock signal and the feedback clock signal of less than the threshold amount.

Claim 9

The programmable logic device of claim 1 wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.

Claim 10

The programmable logic device of claim 1 wherein a clock signal received at a logic block is used as the feedback clock signal.

Claim 11

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein the clock synchronization circuit comprises a delay-locked loop circuit, and the clock synchronization circuit minimizes skew for n clock signals, each of the n clock signals being received at one of n logic blocks.

Claim 12

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein the clock synchronization circuit comprises a delay-locked loop circuit, and the clock synchronization circuit minimizes skew for n clock signals, each of the n clock signals being received at one of n logic blocks.

Claim 13

The programmable logic integrated circuit of claim 10 wherein the clock synchronization circuit comprises: a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; and a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit.

Claim 14

The programmable logic integrated circuit of claim 11 wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 15

The programmable logic integrated circuit of claim 12 wherein the output of the current pump is coupled through a low pass filter to the variable delay circuit.

Claim 16

The programmable logic integrated circuit of claim 11 wherein the control circuit comprises: a delay element, coupled between the synchronized clock output signal and the feedback clock signal.

Claim 17

The programmable logic integrated circuit of claim 11 wherein the control circuit comprises: a macro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the macro phase detect circuit generates a first signal indicating a first phase difference between the reference clock signal and the feedback clock signal of at least a threshold amount; and a micro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the micro phase detect circuit generates a second signal indicating a second phase difference between the reference clock signal and the feedback clock signal of less than the threshold amount.

Claim 18

The programmable logic integrated circuit of claim 10 wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.

Claim 19

The programmable logic integrated circuit of claim 10 wherein a clock signal received at a logic block is used as the feedback clock signal.

Claim 20

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block; a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; and a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit.

Claim 21

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block; a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; and a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit.

Claim 22

The programmable logic integrated circuit of claim 18 wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 23

The programmable logic integrated circuit of claim 19 wherein the output of the current pump is coupled through a low pass filter to the variable delay circuit.

Claim 24

The programmable logic integrated circuit of claim 18 wherein the control circuit comprises: a delay element, coupled between the synchronized clock output signal and the feedback clock signal.

Claim 25

The programmable logic integrated circuit of claim 18 wherein the control circuit comprises: a macro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the macro phase detect circuit generates a first signal indicating a first phase difference between the reference clock signal and the feedback clock signal of at least a threshold amount; and a micro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the micro phase detect circuit generates a second signal indicating a second phase difference between the reference clock signal and the feedback clock signal of less than the threshold amount.

Claim 26

The programmable logic integrated circuit of claim 18 wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.

Claim 27

The programmable logic integrated circuit of claim 18 wherein a clock signal received at a logic block is used as the feedback clock signal.

Claim 28

The programmable logic integrated circuit of claim 20 wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.

Claim 29

The programmable logic integrated circuit of claim 20 wherein a clock signal received at a logic block is used as the feedback clock signal.

Claim 30

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuitry receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.

Claim 31

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuitry receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.

Claim 32

The programmable logic integrated circuit of claim 27 wherein the clock synchronization circuit comprises: a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; and a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit.

Claim 33

The programmable logic integrated circuit of claim 28 wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 34

The programmable logic integrated circuit of claim 29 wherein the output of the current pump is coupled through a low pass filter to the variable delay circuit.

Claim 35

The programmable logic integrated circuit of claim 28 wherein the control circuit comprises: a delay element, coupled between the synchronized clock output signal and the feedback clock signal.

Claim 36

The programmable logic integrated circuit of claim 28 wherein the control circuit comprises: a macro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the macro phase detect circuit generates a first signal indicating a first phase difference between the reference clock signal and the feedback clock signal of at least a threshold amount; and a micro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the micro phase detect circuit generates a second signal indicating a second phase difference between the reference clock signal and the feedback clock signal of less than the threshold amount.

Claim 37

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein a clock signal received at a logic block is used as the feedback clock signal.

Claim 38

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein a clock signal received at a logic block is used as the feedback clock signal.

Claim 39

The programmable logic integrated circuit of claim 33 wherein the clock synchronization circuit comprises: a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; and a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit.

Claim 40

The programmable logic integrated circuit of claim 34 wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 41

The programmable logic integrated circuit of claim 35 wherein the output of the current pump is coupled through a low pass filter to the variable delay circuit.

Claim 42

The programmable logic integrated circuit of claim 34 wherein the control circuit comprises: a delay element, coupled between the synchronized clock output signal and the feedback clock signal.

Claim 43

The programmable logic integrated circuit of claim 34 wherein the control circuit comprises: a macro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the macro phase detect circuit generates a first signal indicating a first phase difference between the reference clock signal and the feedback clock signal of at least a threshold amount; and a micro phase detect circuit, coupled to the reference clock signal and the feedback clock signal, wherein the micro phase detect circuit generates a second signal indicating a second phase difference between the reference clock signal and the feedback clock signal of less than the threshold amount.

Claim 44

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks, wherein the clock synchronization circuit comprises a delay-locked loop circuit, and the clock synchronization circuit minimizes skew for n clock signals, each of the n clock signals being received at one of n logic blocks, wherein the clock synchronization circuit comprises: a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit, wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 45

A programmable logic integrated circuit comprising: an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs; an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array; a reference clock signal; and a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block, wherein the clock synchronization circuit provides a plurality of synchronized clock output signals, each to a different logic block in the array, wherein the clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks, wherein the clock synchronization circuit comprises a delay-locked loop circuit, and the clock synchronization circuit minimizes skew for n clock signals, each of the n clock signals being received at one of n logic blocks, wherein the clock synchronization circuit comprises: a variable delay circuit, receiving the reference clock signal and outputting the synchronized clock output signal; a control circuit, receiving the reference clock signal and the feedback clock signal, and providing a control signal output to the variable delay circuit to adjust a delay provided by the variable delay circuit, wherein the control circuit comprises: a phase-frequency detector, coupled to the reference clock signal and the feedback clock signal, wherein the phase-frequency detector generates an up signal and a down signal; and a current pump, coupled to the up signal and the down signal, wherein an output of the current pump is coupled to the variable delay circuit as the control signal output.

Claim 46

The programmable logic integrated circuit of claims 1, 10, 18, 27, 33, or 39 wherein a logic block comprises: a logical function generator of four variables comprising a combinatorial output; and a register comprising a registered output.

Claim 47

The programmable logic integrated circuit of claim 40 wherein a combinatorial output from a first logic block may be programmably coupled directly to an input of a second logic block without passing through the interconnect structure.

Claim 48

The programmable logic integrated circuit of claim 40 wherein the logic block further comprises a local interconnect structure to programmably couple signals a shorter distance than using the interconnect structure.

Claim 49

The programmable logic integrated circuit of claims 1, 10, 18, 27, 33, or 39 wherein the synchronized clock output is programmably coupled to a look-up table within each of the logic blocks.

Claim 50

The programmable logic integrated circuit of claims 1, 10, 18, 27, 33, or 39 wherein the synchronized clock output is coupled to a register within each of the logic blocks.

Claim 51

The programmable logic integrated circuit of claims 1, 10, 18, 27, 33, or 39 further comprising: a plurality of input-output blocks, programmably coupled to the interconnect structure wherein each input-output block is programmably configurable to be an input driver or an output driver.

Claim 52

A programmable logic device comprising: a plurality of logic array blocks, wherein a logic array block comprises: a logical function generator of four variables comprising a combinatorial output; and a register comprising a registered output; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks; and a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop.

Claim 53

A programmable logic device comprising: a plurality of logic array blocks, wherein a logic array block comprises: a logical function generator of four variables comprising a combinatorial output; and a register comprising a registered output; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks; and a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop.

Claim 54

The programmable logic device of claim 46 wherein a combinatorial output from a first logic block may be programmably coupled directly to an input of a second logic lock without passing through the plurality of programmable interconnect.

Claim 55

The programmable logic device of claim 46 wherein the logic block further comprises a local interconnect structure to programmably couple signals a shorter distance than using the programmable interconnect.

Claim 56

A programmable logic device comprising: a plurality of logic array blocks; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks: a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop; and a plurality of input-output blocks programmably coupled to the programmable interconnect, wherein each input-output block is programmably configurable to be an input driver or an output driver.

Claim 57

A programmable logic device comprising: a plurality of logic array blocks; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks: a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop; and a plurality of input-output blocks programmably coupled to the programmable interconnect, wherein each input-output block is programmably configurable to be an input driver or an output driver.

Claim 58

A programmable logic device comprising: a plurality of logic array blocks; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks; and a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop and the synchronized clock output is programmably coupled to a look-up table within each of the logic blocks.

Claim 59

A programmable logic device comprising: a plurality of logic array blocks; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks; and a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop and the synchronized clock output is programmably coupled to a look-up table within each of the logic blocks.

Claim 60

A programmable logic device comprising: a plurality of logic array blocks; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks; and a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop and the synchronized clock output is coupled to a register within each of the logic blocks.

Claim 61

A programmable logic device comprising: a plurality of logic array blocks; a plurality of programmable interconnect for programmably coupling the plurality of logic array blocks; and a delay lock loop for outputting a synchronized clock output, coupled to the plurality of logic array blocks, locked to an external reference clock signal, wherein the delay lock loop is an analog delay lock loop and the synchronized clock output is coupled to a register within each of the logic blocks.