Externally synchronized programmable device

Claim 2

An external synchronization programmable device comprising: a programmable logic portion having an AND matrix and an OR matrix for implementing a desired logic circuit by programming connections, said logic portion being programmed to generate an internal signal having a phase and a leading edge; means for supplying an external signal having a phase; and a phase comparison circuit for comparing the phase of said external signal with the phase of said internal signal, wherein said phase comparison circuit generates a signal expressing phase lagging and phase leading.

Claim 3

An external synchronization programmable device comprising: a programmable logic portion having an AND matrix and an OR matrix for implementing a desired logic circuit by programming connections, said AND matrix having input signal lines, said logic portion being programmed to generate an internal signal having a phase; means for supplying an external signal having a phase; and a phase comparison circuit for comparing the phase of said external signal with the phase of said internal signal, wherein said phase comparison circuit generates a signal representative of the phase difference between the two signals and supplies a signal expressing whether the phases of said external signal and said internal signal coincide with each other to feed the signal to a predetermined part of said input signal lines of said AND matrix.

Claim 4

An external synchronization programmable device comprising: a programmable logic portion having an AND matrix and an OR matrix for implementing a desired logic circuit by programming connections, said AND matrix having input signal lines, said logic portion being programmed to generate an internal signal having a phase; means for supplying an external signal having a phase; and a phase comparison circuit for comparing the phase of said external signal with the phase of said internal signal, wherein said phase comparison circuit generates a signal representative of the phase difference between the two signals and supplies a signal expressing whether the phases of said external signal and said internal signal coincide with each other to feed the signal to a predetermined part of said input signal lines of said AND matrix.

Claim 5

An external synchronization programmable device according to claim 1, wherein said phase comparison circuit further comprises: a digital phase comparator circuit comprising a plurality of NAND circuits and a plurality of inverter circuits, said circuits arranged so that said phase comparison circuit generates a first logical output signal and a second logical output signal, said output signals being representative of the time width corresponding to the phase difference at the leading edge of said internal signal with respect to said external signal.

Claim 6

The external synchronization programmable device according to claim 3, further comprising a pump circuit comprising: a P-channel MOS transistor; and an N-channel MOS transistor, wherein said pump circuit is responsive to said logical output signals of said phase comparison circuit and generating a high output when both of said output signals are low, a low output when both of said output signals are high, and a high-impedance level when said first and said second output signals are different.

Claim 7

The external synchronization programmable device according to claim 3, wherein said first output signal is low when said phase of said external signal leads said phase of said internal signal; and said second output signal is high when said phase of said external signal lags said phase of said internal signal.

Claim 8

The external synchronization programmable device according to claim 4, further comprising: a phase-locked loop circuit located outside of said programmable device, said phase-locked loop circuit comprising: a low-pass filter outputting a voltage signal responsive to output of said pump circuit, and a voltage-controlled oscillator circuit responsive to said output of said low-pass filter, wherein said voltage-controlled circuit generates a signal having an oscillation frequency corresponding to the voltage of said output of said low-pass filter.

Claim 9

An external synchronization programmable device connected to an external signal having a phase, comprising: an AND matrix; an OR matrix, wherein said AND matrix and said OR matrix can be programmed to form a logic circuit generating at least an internal signal having a phase; a fixed phase comparison circuit for comparing the phase of said internal signal and said external signal; a charge pump circuit for generating an output indicative of the difference between said phases of said internal signal and said external signal; a voltage-controlled oscillator circuit; an active filter responsive to said charge pump circuit and generating an output to control said voltage-controlled oscillator circuit; wherein, said voltage-controlled oscillator circuit generates a signal having a predetermined frequency corresponding to said output of said active filter to synchronize operation of said programmable logic circuit with said external signal.

Claim 10

An external synchronization programmable device connected to an external signal having a phase, comprising: an AND matrix; an OR matrix, wherein said AND matrix and said OR matrix can be programmed to form a logic circuit generating at least an internal signal having a phase; a fixed phase comparison circuit for comparing the phase of said internal signal and said external signal; a charge pump circuit for generating an output indicative of the difference between said phases of said internal signal and said external signal; a voltage-controlled oscillator circuit; an active filter responsive to said charge pump circuit and generating an output to control said voltage-controlled oscillator circuit; wherein, said voltage-controlled oscillator circuit generates a signal having a predetermined frequency corresponding to said output of said active filter to synchronize operation of said programmable logic circuit with said external signal.

Claim 11

The external synchronization programmable device according to claim 7, wherein said active filter further comprises: an amplifier; and a resistor having a predetermined frequency characteristic.

Claim 12

An external synchronization programmable device comprising: a programmable logic portion having an AND matrix and an OR matrix for designing a desired logic circuit by programming connections, said OR matrix having at least a first and second output with a unique phase; and a phase comparison circuit for comparing the phase of said first output with the phase of said second output, wherein said phase comparison circuit generates a signal expressing phase lagging and phase leading.

Claim 13

An external synchronization programmable device comprising: a programmable logic portion having an AND matrix and an OR matrix for designing a desired logic circuit by programming connections, said OR matrix having at least a first and second output with a unique phase; and a phase comparison circuit for comparing the phase of said first output with the phase of said second output, wherein said phase comparison circuit generates a signal expressing phase lagging and phase leading.

Claim 14

The externally synchronized programmable device according to claim 9, wherein said phase comparison circuit further comprises: a plurality of NAND circuits; a plurality of AND circuits; a plurality of inverter circuits; and a plurality of exclusive NOR circuits; wherein said circuits are arranged to generate first and second logical output signals representative of the time width corresponding to the phase difference of said leading edge of said second signal of said OR matrix with respect to the phase of said first signal of said OR matrix.