US4808937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked loop for a modem
Assignee: Telogy Networks Inc
•
Filing: 1986-07-15
•
Granted: 1989-02-28
•
Expires: 2006-07-15
Abstract
Abstract A modem and an improved phase-locked loop used in the modem. A presettable counter (251) generates the desired signal (TXCLKOUT). The reference input clock signal (TXCLKIN) and the generated clock signal (TXCLKOUT) are compared by an exclusive-OR gate (254). The output of the gate (254) is sampled by two flip-flops (256,266) before and after a rising edge of the TXCLKOUT signal. If the TXCLKIN and TXCLKOUT signals differ by more than a desired phase window a logic circuit (264) adjusts the preset inputs of the counter (251) so that the TXCLKIN and TXCLKOUT signals are in phase within the desired phase window.
Inventors
- 👤 German E. Correa
- 👤 Cynthia J. Correa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:51
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042; H04L27/00; H04L27/02; H04L27/08; H04L27/18; H04L27/20; H04L27/2032; H04L27/2053; H04L27/206; H04L27/2067; H04L27/2071; H04L27/32; H04L27/34; H04L27/36; H04L27/362; H04L7/02; H04L7/033; H04L7/0334; H04L9/00; H04L9/40; H04L7/0331
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
129 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said input signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means.
Claim 2
Independent Claim
129 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said input signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means.
Claim 3
Independent Claim
139 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said input signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at second sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means; wherein said programmable clock means comprise a presettable counter.
Claim 4
Independent Claim
139 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said input signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at second sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means; wherein said programmable clock means comprise a presettable counter.
Claim 5
Independent Claim
138 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said output signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at second sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means wherein said comparator means comprises an exclusive-OR gate.
Claim 6
Independent Claim
138 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said output signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at second sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means wherein said comparator means comprises an exclusive-OR gate.
Claim 7
Independent Claim
158 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said input signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at second sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means; wherein said first sampling points occur prior to predetermined transitions of said output signal and said second sampling points occur after said predetermined transitions of said output signal.
Claim 8
Independent Claim
158 words
An apparatus for generating an output signal which is phase-locked to an input signal, comprising: a reference clock; programmable clock means responsive to said reference clock and to error correction information for generating said output signal; comparator means for providing a first signal responsive to said output signal and said input signal; first sampling means for providing a first sampled signal by sampling said first signal at first sampling points; second sampling means for providing a second sampled signal by sampling said first signal at second sampling points, said second sampling points being displaced from said first sampling points by a predetermined sampling time offset; and processing means responsive to said first sampled signal and said second sampled signal for providing said error correction information to said programmable clock means; wherein said first sampling points occur prior to predetermined transitions of said output signal and said second sampling points occur after said predetermined transitions of said output signal.
Claim 9
Dependent Claim
108 words
An improved method for generating an output signal which is phase-locked to an input signal, comprising: generating said output signals; comparing said output signal to said input signal at a first point before a predetermined transition of said output signal to generate a first signal; comparing said output signal to said input signal at second point after said predetermined transition of said output signal to generate a second signal; comparing said first sampled signal with said second sampled signal to determine a relative phase difference between said output signal and said input signal; and adjusting said output signal in a manner tending to minimize said relative phase difference.
Claim 10
Dependent Claim
108 words
An improved method for generating an output signal which is phase-locked to an input signal, comprising: generating said output signals; comparing said output signal to said input signal at a first point before a predetermined transition of said output signal to generate a first signal; comparing said output signal to said input signal at second point after said predetermined transition of said output signal to generate a second signal; comparing said first sampled signal with said second sampled signal to determine a relative phase difference between said output signal and said input signal; and adjusting said output signal in a manner tending to minimize said relative phase difference.
Claim 11
Dependent Claim
18 words
The improved method of claim 5 wherein said predetermine transition is a rising edge of said output signal.
Claim 12
Dependent Claim
25 words
The method of claim 5 wherein said output signal is adjusted by changing the phases of said output signal by a predetermined phase step size.
References Cited (Backward Citations)
US4280099A
Cited
US4455661A
Cited
US4400817A
Cited
US4538119A
Cited
US4472818A
Cited
US4488294A
Cited
WO1985000255A1
Cited
EP0142302A2
Cited
EP0171856A1
Cited
US4680780A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |