US5815016A
Expired / Lapsed
US
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Phase-locked delay loop for clock correction
Assignee: Xilinx Inc
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Filing: 1996-06-14
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Granted: 1998-09-29
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Expires: 2016-06-14
Abstract
Abstract A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship. In one embodiment both the positive and negative edges of a clock signal are corrected. As another feature, if correction is consistently in the same direction an error flag is generated.
Inventors
- 👤 Charles R. Erickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:00
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/085
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
300 words
A phase-locked loop, comprising: a positive phase detector including a first terminal connected to receive a reference input clock signal, and a second terminal connected to receive an output clock feedback signal, said positive phase detector producing a positive phase detector output signal indicative of a phase difference between a positive edge of said reference input clock signal and a positive edge of said output clock feedback signal; at least one voltage controlled delay element connected to receive said positive phase detector output signal, said voltage controlled delay element producing a positive output clock signal with a positive edge that is delayed from said positive edge of said reference input clock signal by an amount related to said positive phase detector output signal; a negative phase detector including a first terminal connected to receive said reference input clock signal, and a second terminal connected to receive said output clock feedback signal, said negative phase detector producing a negative phase detector output signal indicative of a phase difference between a negative edge of said reference input clock signal and a negative edge of said output clock feedback signal; at least one voltage controlled delay element connected to receive said negative phase detector output signal, said voltage controlled delay element producing a negative output clock signal with a negative edge that is delayed from said negative edge of said reference input clock signal by an amount related to said negative phase detector output signal; and an output clock signal generator for generating an output clock signal having a positive clock edge in phase with said positive edge of said positive output clock signal and a negative clock edge in phase with said negative edge of said negative output clock signal, said output clock feedback signal being derived from said output clock signal.
Claim 2
Dependent Claim
300 words
A phase-locked loop, comprising: a positive phase detector including a first terminal connected to receive a reference input clock signal, and a second terminal connected to receive an output clock feedback signal, said positive phase detector producing a positive phase detector output signal indicative of a phase difference between a positive edge of said reference input clock signal and a positive edge of said output clock feedback signal; at least one voltage controlled delay element connected to receive said positive phase detector output signal, said voltage controlled delay element producing a positive output clock signal with a positive edge that is delayed from said positive edge of said reference input clock signal by an amount related to said positive phase detector output signal; a negative phase detector including a first terminal connected to receive said reference input clock signal, and a second terminal connected to receive said output clock feedback signal, said negative phase detector producing a negative phase detector output signal indicative of a phase difference between a negative edge of said reference input clock signal and a negative edge of said output clock feedback signal; at least one voltage controlled delay element connected to receive said negative phase detector output signal, said voltage controlled delay element producing a negative output clock signal with a negative edge that is delayed from said negative edge of said reference input clock signal by an amount related to said negative phase detector output signal; and an output clock signal generator for generating an output clock signal having a positive clock edge in phase with said positive edge of said positive output clock signal and a negative clock edge in phase with said negative edge of said negative output clock signal, said output clock feedback signal being derived from said output clock signal.
Claim 3
Dependent Claim
169 words
A phase-locked loop, comprising: a phase detector including a first terminal connected to receive a reference input clock signal, and a second terminal connected to receive an output clock feedback signal, said phase detector producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said output clock feedback signal; at least one voltage controlled delay element connected to receive said phase detector output signal, said voltage controlled delay element producing an output clock signal that is in a selected phase relationship with said reference input clock signal, and that is delayed relative to said reference input clock signal; and counting means for detecting repeated phase errors in the same direction and for generating a flag when a number of repeated phase errors in the same direction exceeds a limit; wherein said output clock feedback signal received at said second terminal of said phase detector is derived from said output clock signal generated by said at least one voltage controlled delay element.
Claim 4
Dependent Claim
169 words
A phase-locked loop, comprising: a phase detector including a first terminal connected to receive a reference input clock signal, and a second terminal connected to receive an output clock feedback signal, said phase detector producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said output clock feedback signal; at least one voltage controlled delay element connected to receive said phase detector output signal, said voltage controlled delay element producing an output clock signal that is in a selected phase relationship with said reference input clock signal, and that is delayed relative to said reference input clock signal; and counting means for detecting repeated phase errors in the same direction and for generating a flag when a number of repeated phase errors in the same direction exceeds a limit; wherein said output clock feedback signal received at said second terminal of said phase detector is derived from said output clock signal generated by said at least one voltage controlled delay element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |