Phase-locked loop and resulting frequency multiplier

Claim 2

A phase-locked loop circuit (10) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal (CTL); a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); wherein said delay circuit means introduces a controllable phase delay between the input signal (CL) applied to its first input and the negative feedback signal (FDB) produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; and wherein the digital command device is an up-down counter (12) having first and second inputs, and the comparator output signals (INC, DEC) are applied to the respective first and second inputs (12a, 12b) of the up-down counter.

Claim 3

A phase-locked loop circuit (10) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal (CTL); a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); wherein said delay circuit means introduces a controllable phase delay between the input signal (CL) applied to its first input and the negative feedback signal (FDB) produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; wherein the delay circuit means (13) is composed of an integral number (N) of delay elements (130-137) connected in series, each delay element producing equal respective delays at said at least one output and the total delay of the delay means encompasses the time interval between two recurring predetermined edges of the input signal (CL); and wherein the digital command device is an up-down counter (12) having first and second inputs, and the comparator output signals (INC, DEC) are applied to the respective first and second inputs (12a, 12b) of the up/down counter.

Claim 4

A phase-locked loop circuit (10) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal (CTL); a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); wherein said delay circuit means introduces a controllable phase delay between the input signal (CL) applied to its first input and the negative feedback signal (FDB) produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; wherein the delay circuit means (13) is composed of an integral number (N) of delay elements (130-137) connected in series, each delay element producing equal respective delays at said at least one output and the total delay of the delay means encompasses the time interval between two recurring predetermined edges of the input signal (CL); and wherein the digital command device is an up-down counter (12) having first and second inputs, and the comparator output signals (INC, DEC) are applied to the respective first and second inputs (12a, 12b) of the up/down counter.

Claim 5

A phase-locked loop circuit (10) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal (CTL); a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); wherein said delay circuit means introduces a controllable phase delay between the input signal (CL) applied to its first input and the negative feedback signal (FDB) produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; wherein the delay circuit means (13) is composed of an integral number (N) of delay elements (130-137) connected in series, each delay element producing equal respective delays at said at least one output and the total delay of the delay means encompasses the time interval between two recurring predetermined edges of the input signal (CL); and wherein the phase comparator (11) includes at least one pair of flip flops (14, 15) sensitive to a predetermined recurring edge of the input signal (CL), said flip flops including clock inputs and data inputs, means connecting the data inputs to respective receive the input signal (CL) and the negative feedback signal (FB), and means connecting the clock inputs to respectively receive the negative feedback signal and the input signal.

Claim 6

A phase-locked loop circuit (10) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal (CTL); a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); wherein said delay circuit means introduces a controllable phase delay between the input signal (CL) applied to its first input and the negative feedback signal (FDB) produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; wherein the delay circuit means (13) is composed of an integral number (N) of delay elements (130-137) connected in series, each delay element producing equal respective delays at said at least one output and the total delay of the delay means encompasses the time interval between two recurring predetermined edges of the input signal (CL); and wherein the phase comparator (11) includes at least one pair of flip flops (14, 15) sensitive to a predetermined recurring edge of the input signal (CL), said flip flops including clock inputs and data inputs, means connecting the data inputs to respective receive the input signal (CL) and the negative feedback signal (FB), and means connecting the clock inputs to respectively receive the negative feedback signal and the input signal.

Claim 7

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a first output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit means (13) includes an integral number (N) of delay elements (130-137) connected in series and producing equal respective delays sharing the time interval between two recurring predetermined edges of the input signal (CL), the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and means for connecting the negative feedback signal from the output of the last delay element (137).

Claim 8

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a first output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit means (13) includes an integral number (N) of delay elements (130-137) connected in series and producing equal respective delays sharing the time interval between two recurring predetermined edges of the input signal (CL), the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and means for connecting the negative feedback signal from the output of the last delay element (137).

Claim 9

The multiplier as defined by claim 4, wherein the input signal (CL) is a square signal having adjacent leading and trailing edges forming the recurring predetermined edges of the input signal, and the phase comparator includes means sensitive to said leading and trailing edges.

Claim 10

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a first output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; wherein the logical adder (16) is a tree circuit of EXCLUSIVE OR gates; and wherein the delay circuit means (13) includes an integral number (N) of delay elements (130-137) connected in series and producing equal respective delays sharing the time interval between two recurring predetermined edges of the input signal (CL), the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and means for sampling the negative feedback signal from the output of the last delay element (137).

Claim 11

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a first output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; wherein the logical adder (16) is a tree circuit of EXCLUSIVE OR gates; and wherein the delay circuit means (13) includes an integral number (N) of delay elements (130-137) connected in series and producing equal respective delays sharing the time interval between two recurring predetermined edges of the input signal (CL), the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and means for sampling the negative feedback signal from the output of the last delay element (137).

Claim 12

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a first output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit means (13) is composed on an integral number (N) of delay elements (130-137) connected in series, the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and further including selection device means for connecting the negative feedback signal (FB) from one of the delay elements and disconnecting from the delay element in which the negative feedback signal is connected the following series connected delay elements.

Claim 13

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a first output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit means (13) is composed on an integral number (N) of delay elements (130-137) connected in series, the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and further including selection device means for connecting the negative feedback signal (FB) from one of the delay elements and disconnecting from the delay element in which the negative feedback signal is connected the following series connected delay elements.

Claim 14

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a fist output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; wherein the logical adder (16) is a tree circuit of EXCLUSIVE OR gates; and wherein the delay circuit means (13) is composed of an integral number (N) of delay elements (130-137) connected in series, the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and further including selection device means for connecting the negative feedback signal (FB) from one of the delay elements and disconnecting from the delay element in which the negative feedback signal is connected the following series connected delay elements.

Claim 15

A frequency multiplier (20) comprising: a phase comparator (11) for comparing an input signal (CL) with a negative feedback signal (FB) to produce comparator output signals (INC, DEC); delay circuit means (13) having first and second inputs and a plurality of outputs, for producing at a fist output the negative feedback signal (FB) and at the remaining plurality of outputs variable phase delayed signals exhibiting equal delays therebetween, said first input connected to receive said input signal (CL), said second input connected to receive a command signal (CTL), said remaining plurality of outputs connected to a logical adder; a digital phase command device (12) connected to the phase comparator and to the delay circuit means for producing the command signal (CTL) responsive to said comparator output signals (INC, DEC) and for providing the command signal to said second input of said delay circuit means (13); said logical adder (16) connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; wherein the logical adder (16) is a tree circuit of EXCLUSIVE OR gates; and wherein the delay circuit means (13) is composed of an integral number (N) of delay elements (130-137) connected in series, the delayed input signal comprises delayed output signals (CL0-CL7) from the respective delay elements, and further including selection device means for connecting the negative feedback signal (FB) from one of the delay elements and disconnecting from the delay element in which the negative feedback signal is connected the following series connected delay elements.

Claim 16

The multiplier as defined by claim 8, wherein the logical adder (16) assigns equal propagation times between the delayed input signal applied to the tree circuit and the output (20b) of the tree circuit.