US3587043A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Character parity synchronizer
Assignee: RCA Corp
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Filing: 1969-04-29
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Granted: 1971-06-22
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Expires: 1989-04-29
Abstract
Abstract Character synchronizing bits having a predetermined binary level are generated from a single serial stream of binary parity encoded characters, and once having been generated, continue to be produced independent of the encoded characters for thereafter synchronously processing the encoded characters. Timing disparities between the synchronizing bits and the encoded characters are rapidly detected and a new stream of synchronizing bits is generated when loss of synchronization is manifested.
Inventors
- 👤 Carl Michael Mengani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:38
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H04L7/04; H04L7/048
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
116 words
In combination, first means for receiving n-bit binary parity encoded characters and for determining when said encoded characters meet a preestablished parity requirement, said first means being responsive to said characters for generating a serial stream of bits, said generated stream of bits including a parity representing bit in a predetermined ordinal bit position for each encoded character meeting said parity requirement, second means for generating a sequence of n-bits and for comparing said sequence of generated n-bits in time coincidence with said generated serial stream of bits, said second meanS operating to recirculate only that one of said sequence of generated n-bits which coincides in time with said parity representing bit as a self-clocking bit.
Claim 2
Dependent Claim
116 words
In combination, first means for receiving n-bit binary parity encoded characters and for determining when said encoded characters meet a preestablished parity requirement, said first means being responsive to said characters for generating a serial stream of bits, said generated stream of bits including a parity representing bit in a predetermined ordinal bit position for each encoded character meeting said parity requirement, second means for generating a sequence of n-bits and for comparing said sequence of generated n-bits in time coincidence with said generated serial stream of bits, said second meanS operating to recirculate only that one of said sequence of generated n-bits which coincides in time with said parity representing bit as a self-clocking bit.
Claim 3
Dependent Claim
55 words
The combination as claimed in claim 1, and wherein said second means includes a recirculating register means responsive to the generating of said self-clocking bit to cause said self-clocking bit to be recirculated in said register means independently of the operation of said parity representing bit generating means once said self-clocking bit has been generated.
Claim 4
Dependent Claim
84 words
The combination as claimed in claim 2, and including, means responsive to said parity representing bits and to said self-clocking bit for generating an error signal only upon a given number of out-of-time coincidence conditions existing therebetween, said means for generating said self-clocking bit including further means responsive to said error signal to erase said self-clocking bit and cause said means for generating said self-clocking bit to again generate said sequence of n-bits for time coincidence comparison with said generated serial stream of bits.
Claim 5
Dependent Claim
177 words
In combination, first means for receiving n-bit binary parity encoded characters and for determining when said encoded characters meet a preestablished parity requirement, said first means being responsive to said characters for generating a serial stream of bits, said generated stream of bits including a parity representing bit in a predetermined ordinal bit position for each encoded character meeting a preestablished parity requirement, a shift register and means for operating said register to produce a sequence of n-bits, said register including n-stages, each capable of assuming one of two binary states, means for comparing said sequence of n-bits in time coincidence with said serial stream of bits and for recirculating to said register only that one of said sequence of n-bits as a self-clocking bit which is in time coincidence with said parity representing bits, means for detecting the state of said n-stages when said self-clocking bit is recirculating through said register to cause said self-clocking bit when once generated to recirculate through said register independent of said parity representing bit generating means and said comparing means.
Claim 6
Dependent Claim
177 words
In combination, first means for receiving n-bit binary parity encoded characters and for determining when said encoded characters meet a preestablished parity requirement, said first means being responsive to said characters for generating a serial stream of bits, said generated stream of bits including a parity representing bit in a predetermined ordinal bit position for each encoded character meeting a preestablished parity requirement, a shift register and means for operating said register to produce a sequence of n-bits, said register including n-stages, each capable of assuming one of two binary states, means for comparing said sequence of n-bits in time coincidence with said serial stream of bits and for recirculating to said register only that one of said sequence of n-bits as a self-clocking bit which is in time coincidence with said parity representing bits, means for detecting the state of said n-stages when said self-clocking bit is recirculating through said register to cause said self-clocking bit when once generated to recirculate through said register independent of said parity representing bit generating means and said comparing means.
Claim 7
Dependent Claim
90 words
The combination as claimed in claim 4 and including, means for comparing said self-clocking bits in time coincidence with said parity representing bits to produce an error signal only upon a given number of out-of-time coincidence conditions existing therebetween, said means for detecting the state of said n-stages including further means responsive to said error signal to block said self-clocking bit and cause said sequence of n-bits to again be compared by said comparing means in time coincidence with said serial stream of bits to produce a retimed self-clocking bit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |