Phase shift circuit utilizing a variable time delay line

Claim 2

A phase modulator comprised of: an input signal to be phase modulated; a clock-controlled delay line used to provide a time delay of said input signal; a phase detector which measures the phase difference between said input and output of said clock-controlled delay line, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a time-varying reference voltage; said time-varying reference voltage being a function of a desired amount phase modulation; said error voltage being applied to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set said time delay of said clock-controlled delay line; output of said clock-controlled delay line being phase modulated from said input signal by the desired amount.

Claim 3

An analog phase shifter comprised of: an analog input signal to be phase shifted; a clock-controlled analog delay line used to provide a time delay of said analog input signal; a phase detector which measures the phase difference between said analog input signal and output of said clock-controlled analog delay line, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing a desired phase shift; said error voltage being applied to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set said time delay of said clock-controlled analog delay line; output of said clock-controlled analog delay line being time delayed from said analog input signal to produce the desired phase shift.

Claim 4

An analog phase shifter comprised of: an analog input signal to be phase shifted; a clock-controlled analog delay line used to provide a time delay of said analog input signal; a phase detector which measures the phase difference between said analog input signal and output of said clock-controlled analog delay line, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing a desired phase shift; said error voltage being applied to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set said time delay of said clock-controlled analog delay line; output of said clock-controlled analog delay line being time delayed from said analog input signal to produce the desired phase shift.

Claim 5

The analog phase shifter of claim 2 comprising: said integrator comprised of an operational amplifier with said error voltage connected to a resistor which is connected to the inverting input of said operational amplifier; a capacitor connecting said inverting input and output of said operational amplifier; noninverting input of said operational amplifier connected to electrical ground; a single pole, single throw switch serially connected to a voltage source; said voltage source and said switch being connected in parallel with said capacitor; said voltage source polarity and magnitude set so as to drive said voltage controlled oscillator at maximum allowable clock rate of said clock-controlled analog delay line when said switch is closed; said switch being then opened allows the time delay of said clock-controlled analog delay line to increase from a minimum value to that required to generate said desired phase shift. wherein the smallest time delay corresponding to the desired phase shift is obtained.

Claim 6

A delay time comprising a coupled plurality of analog phase shifters coupled in series wherein each phase shifter is comprised of: an analog input terminal to receive an analog input signal to be phased shifted; a clock-controlled analog delay line used to provide a time delay of said analog input signal; a phase detector which measures the phase difference between said analog input signal and output of said clock-controlled analog delay line, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing a desired delay; said error voltage being applied to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set said time delay of said clock-controlled analog delay line; output of said clock-controlled analog delay line being time delayed from said analog input signal by the desired delay.

Claim 7

A delay time comprising a coupled plurality of analog phase shifters coupled in series wherein each phase shifter is comprised of: an analog input terminal to receive an analog input signal to be phased shifted; a clock-controlled analog delay line used to provide a time delay of said analog input signal; a phase detector which measures the phase difference between said analog input signal and output of said clock-controlled analog delay line, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing a desired delay; said error voltage being applied to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set said time delay of said clock-controlled analog delay line; output of said clock-controlled analog delay line being time delayed from said analog input signal by the desired delay.

Claim 8

A digital phase shifter comprised of: a digital input signal to be phase shifted; a clock-controlled shift register which delays said digital input signal; a phase detector which measures the phase difference between said digital input signal and output of said clock-controlled shift register, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing a desired phase shift; said error voltage connected to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set the delay of said clock-controlled shift register; output of said clock-controlled shift register being delayed from said digital input signal by the desired phase shift.

Claim 9

A digital phase shifter comprised of: a digital input signal to be phase shifted; a clock-controlled shift register which delays said digital input signal; a phase detector which measures the phase difference between said digital input signal and output of said clock-controlled shift register, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing a desired phase shift; said error voltage connected to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set the delay of said clock-controlled shift register; output of said clock-controlled shift register being delayed from said digital input signal by the desired phase shift.

Claim 10

The digital phase shifter of claim 5 comprising: said integrator is comprised of an operational amplifier with said error voltage connected to a resistor which is connected to the inverting input of said operational amplifier; a capacitor connecting said inverting input and output of said operational amplifier; noninverting input of said operational amplifier connected to electrical ground; a single pole, single throw switch serially connected to a voltage source; said voltage source and said switch being connected in parallel with said capacitor; said voltage source polarity and magnitude set so as to drive said voltage controlled oscillator at maximum allowable clock rate of said clock-controlled shift register when said switch is closed; said switch being then opened allows the time delay of said clock-controlled shift register to increase from a minimum value to that required to generate said desired phase shift; wherein the smallest time delay corresponding to the desired phase shift is obtained.

Claim 11

A digital delay line comprising a plurality of digital phase shifters coupled in series wherein each phase shifter is comprised of: a digital input signal terminal receiving a digital input signal to be phase shifted; a clock-controlled shift register which delays said digital input signal; a phase detector which measures the phase difference between said digital input signal and output of said clock-controlled shift register, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing the desired phase shift; said error voltage connected to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set the delay of said clock-controlled shift register; output of said clock-controlled shift register being phase shifted from said digital input signal by the desired phase shift.

Claim 12

A digital delay line comprising a plurality of digital phase shifters coupled in series wherein each phase shifter is comprised of: a digital input signal terminal receiving a digital input signal to be phase shifted; a clock-controlled shift register which delays said digital input signal; a phase detector which measures the phase difference between said digital input signal and output of said clock-controlled shift register, output of said phase detector being a voltage that is a function of said phase difference; a differential operational amplifier generating an error voltage by comparing the output of said phase detector and a reference voltage representing the desired phase shift; said error voltage connected to the input of an integrator; output of said integrator being a feedback control signal; said feedback control signal being applied to the input of a voltage-controlled oscillator; output of said voltage controlled oscillator being a square wave used to set the delay of said clock-controlled shift register; output of said clock-controlled shift register being phase shifted from said digital input signal by the desired phase shift.