US5389843A
Expired / Lapsed
US
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Simplified structure for programmable delays
Assignee: Tektronix Inc
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Filing: 1992-08-28
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Granted: 1995-02-14
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Expires: 2012-08-28
Abstract
Abstract A programmable delay circuit with a simplified structure conserves parts and provides for simplified programmability. In this structure, N delay stages (1-N) each include delay elements (10,26, . . . ,80) that produce delay times that are related as powers of two and are connected by two-input multiplexers (12,22, . . . ,82). The two-input multiplexers select between the input and output of the delay element in their stage, and are collectively controlled by N-bits of delay selection signals that are connected so that less significant bits control multiplexers associated with delay elements producing shorter delays and more significant bits control multiplexers associated with delay elements producing longer delays in a monotonic correspondence. The resulting structure conserves parts and produces an overall delay time that is directly proportional to the binary value used to control the multiplexers. Alternative embodiments are disclosed in which delay elements are related as powers of an arbitrary base number Y instead of two, but this embodiment does not provide all possible delay values and the delay provided is not proportional to the value of the binary bits used for control.
Inventors
- 👤 David J. McKinney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:10
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
215 words
A programmable variable delay circuit comprising a plurality (1-N) of delay stages connected in series, with each delay stage comprising: a delay element (10,20, . . . ,80) having an input and an output, with the delay element associated with each different delay stage providing a characteristic delay time that is an integral power of a base number Y of a unit characteristic delay time t of a shortest delay element, with each delay stage producing a different delay and the delays associated with the plurality of delay stages including delays corresponding to t times each integral power of Y from 0 to N-1; and selecting means (12,22, . . . ,82) having two inputs, for selecting as an output of a particular stage either the input or the output of that stage's delay element; and the programmable variable delay circuit further comprising N-bits of delay selection signals, with the delay selection signals being connected to the selecting means of the plurality of delay stages such that less significant bits are connected to selection means associated with shorter delays and more significant bits are connected to selection means associated with longer delays in a monotonic correspondence, so that digital values applied to the delay selection signals produce proportional cumulative delays from the variable delay circuit.
Claim 2
Dependent Claim
215 words
A programmable variable delay circuit comprising a plurality (1-N) of delay stages connected in series, with each delay stage comprising: a delay element (10,20, . . . ,80) having an input and an output, with the delay element associated with each different delay stage providing a characteristic delay time that is an integral power of a base number Y of a unit characteristic delay time t of a shortest delay element, with each delay stage producing a different delay and the delays associated with the plurality of delay stages including delays corresponding to t times each integral power of Y from 0 to N-1; and selecting means (12,22, . . . ,82) having two inputs, for selecting as an output of a particular stage either the input or the output of that stage's delay element; and the programmable variable delay circuit further comprising N-bits of delay selection signals, with the delay selection signals being connected to the selecting means of the plurality of delay stages such that less significant bits are connected to selection means associated with shorter delays and more significant bits are connected to selection means associated with longer delays in a monotonic correspondence, so that digital values applied to the delay selection signals produce proportional cumulative delays from the variable delay circuit.
Claim 3
Dependent Claim
235 words
A programmable variable delay circuit comprising a plurality (1-N) of delay stages connected in series, with each delay stage comprising: a delay element (10,20, . . . ,80) having an input and an output, with the delay element associated with each different delay stage providing a characteristic delay time that is an integral power of two of a unit characteristic delay time t of a shortest delay element, with each delay stage producing a different delay and the delays associated with the plurality of delay stages including delays corresponding to t times each integral power of two from 0 to N-1; and selecting means (12,22, . . . ,82) having two inputs, for selecting as an output of a particular stage either the input or the output of that stage's delay element, so that by suitable control of the signal selecting means any combination of delays from 0 to (2 N -1)*t may be obtained; and the programmable variable delay circuit further comprising N-bits of delay selection signals, with the delay selection signals being connected to the selecting means of the plurality of delay stages such that less significant bits are connected to selection means associated with shorter delays and more significant bits are connected to selection means associated with longer delays in a monotonic correspondence, so that digital values applied to the delay selection signals produce proportional cumulative delays from the variable delays circuit.
Claim 4
Dependent Claim
235 words
A programmable variable delay circuit comprising a plurality (1-N) of delay stages connected in series, with each delay stage comprising: a delay element (10,20, . . . ,80) having an input and an output, with the delay element associated with each different delay stage providing a characteristic delay time that is an integral power of two of a unit characteristic delay time t of a shortest delay element, with each delay stage producing a different delay and the delays associated with the plurality of delay stages including delays corresponding to t times each integral power of two from 0 to N-1; and selecting means (12,22, . . . ,82) having two inputs, for selecting as an output of a particular stage either the input or the output of that stage's delay element, so that by suitable control of the signal selecting means any combination of delays from 0 to (2 N -1)*t may be obtained; and the programmable variable delay circuit further comprising N-bits of delay selection signals, with the delay selection signals being connected to the selecting means of the plurality of delay stages such that less significant bits are connected to selection means associated with shorter delays and more significant bits are connected to selection means associated with longer delays in a monotonic correspondence, so that digital values applied to the delay selection signals produce proportional cumulative delays from the variable delays circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |