Data reordering system

Claim 1

A circuit for reordering a set of N input coefficients stored in a serial access input register in reverse binary order to normal binary order in a serial access output register, comprising: means for clocking data from said input register and into said output register, said clocking means having a period t; a plurality of delay circuits having progressively decreasing delay periods, said delay periods equal to (N/2-1)t, (N/4-2)t, (N/8-4)t, etc.; and a plurality of switching means connecting each circuit stage including said delay circuits and said input and output registers in series, said switching means alternately having: a. an A position connecting coefficients received from the preceding circuit stage to said delay circuit and coefficients from said delay circuit to the succeeding circuit stage, or b. a B position connecting coefficients received from the preceding circuit stage to the succeeding circuit stage and coefficients from said delay circuit for recirculation through said delay circuit; and means for driving said switching means between said A and B positions in a predetermined sequence as follows: a. for the switching means associated with said (N/2-1)t delay, said switching means are maintained in said A position for a period of (N/2)t, then switched in a sequence B,A,B,A,B . . ., remaining in each position for a period t, until a period of (N/2)t has elapSed, then repeat the sequence, beginning with the A position for a period of (N/2)t; b. for the switching means associated with said (N/4-2)t delay, said switching means are maintained in said A position for a period of (N/4)t, then switched in a sequence B,B,A,A,B,B,A,A . . . , remaining in each position for a period t, until a period of (N/4)t has elapsed, then repeat the sequence, beginning with the A position for a period of (N/4)t; c. for the switching means associated with said (N/8-4)t delay, said switching means are maintained in said A position for a period of (N/8)t, then switched in a sequence B,B,B,B,A,A,A,A, B,B,B,B . . . , remaining in each position for a period t, until a period of (N/8)t has elapsed, then repeat the sequence, beginning with A position for a period of (N/8)t; d. and, following the same progressive order, decreasing the period for maintenance in the A position and the B to A switching sequence by a factor of two for each successive delay circuit and increasing the duration of the B and A positions during the switching sequence by a factor of two for each successive delay circuit, for each of the remaining delay circuits.

Claim 9

A method of reordering serially available input coefficients from a first binary order to a second binary order, comprising: conducting first selected ones of said input coefficients through a time delay apparatus once; conducting second selected ones of said input coefficients through said time delay apparatus twice; and conducting third selected ones of said input coefficients to bypass said time delay apparatus.

Claim 10

A method of reordering serially available input coefficients from a first binary order to a second binary order, comprising: conducting first selected ones of said input coefficients through a time delay apparatus once; conducting second selected ones of said input coefficients through said time delay apparatus twice; and conducting third selected ones of said input coefficients to bypass said time delay apparatus.