Electronic desk top calculator having a delay line and automatic decimal alignment

Claim 2

An electronic calculator comprising a memory having a plurality of registers for storing data, each of said registers having an ordered plurality of digit positions, an arithmetic and control unit coupled to said memory for processing said data, an entry means coupled to said memory for entering data into said registers, and means coupled to said arithmetic and control unit for decimally aligning said data in said registers, said lastnamed means including: a manually actuatable switch for establishing a dEcimal point reference position intermediate adjacent ones of said digit positions in said registers; a counter coupled to said switch for storing a numerical value related to the state of said switch; and means coupled to said counter for shifting the data within at least one of said registers a number of digit positions determined by said numerical value in said counter, whereby said data is aligned relative to said decimal point reference position.

Claim 3

The calculator of claim 1 wherein said entry means includes a decimal point key; and said decimal aligning means includes means coupled to said decimal point key and responsive to the actuation thereof for enabling said counter to be incremented in response to the entry of a digit thereafter.

Claim 4

The calculator of claim 1 further including display means coupled to said switch for indicating said decimal point reference position.

Claim 5

The calculator of claim 1 wherein said entry means includes a plurality of function keys for generating signals specifying data processing functions to be performed by said arithmetic and control unit, and said decimal aligning means includes means coupled to at least one of said function keys for enabling said shifting means in response to the generation of the function signal corresponding to said at least one of said function keys.

Claim 6

The calculator of claim 4 wherein said at least one of said function keys includes an ENTER key.

Claim 7

The calculator of claim 1 wherein said decimal aligning means includes means coupled to said shifting means for incrementing said counter for each single position shift of said data within said at least one of said registers.

Claim 8

The calculator of claim 1 wherein said decimal aligning means further includes means coupled to said counter for disabling said shifting means in response to the occurrence of a predetermined setting in said counter.

Claim 9

The calculator of claim 1 wherein said at least one of said registers includes the entry register of said memory.

Claim 10

In an electronic calculator, the combination comprising: memory means for cyclically channelling data in the form of digit words through a closed loop; means for displaying said data in accordance with an order of significance to form register words arranged in a stack; means coupled to said display means and said memory means for synchronizing the operation therebetween; means coupled to said display means for providing a decimal point reference for said register words; and means coupled to said memory means for aligning said register words in said stack about said decimal point reference.

Claim 11

In an electronic calculator, the combination comprising: memory means for cyclically channelling data in the form of digit words through a closed loop; means for displaying said data in accordance with an order of significance to form register words arranged in a stack; means coupled to said display means and said memory means for synchronizing the operation therebetween; means coupled to said display means for providing a decimal point reference for said register words; and means coupled to said memory means for aligning said register words in said stack about said decimal point reference.

Claim 12

The calculator of claim 9 further including an arithmetic unit coupled to said memory means for combining a plurality of said register words into a single register word by arithmetic process, and means coupled to said arithmetic unit and responsive to the production of said single register word for enabling said aligning means to align said single register word about said decimal point reference.

Claim 13

A electronic calculating device comprising a recirculating memory for serially recirculating a field word of data; an arithmetic unit coupled to said recirculating memory for performing data handling and arithmetic operations on said data, said arithmetic unit comprising a plurality of single character registers, selected ones of said plurality of registers being interconnected to form a subplurality of said registers for providing a normal path for progression of said data through said arithmetic unit, at least one other of said registers being interconnected between a pair of said subplurality of registers to provide alternate paths for enabling modification of said field word; and control means coupled to said arithmetic unit for controlling the path of said data through said arithmetic unit.

Claim 14

A electronic calculating device comprising a recirculating memory for serially recirculating a field word of data; an arithmetic unit coupled to said recirculating memory for performing data handling and arithmetic operations on said data, said arithmetic unit comprising a plurality of single character registers, selected ones of said plurality of registers being interconnected to form a subplurality of said registers for providing a normal path for progression of said data through said arithmetic unit, at least one other of said registers being interconnected between a pair of said subplurality of registers to provide alternate paths for enabling modification of said field word; and control means coupled to said arithmetic unit for controlling the path of said data through said arithmetic unit.

Claim 15

The device of claim 11 wherein said subplurality of registers includes first and second registers; said first regiSter being connected in parallel to said second register; said at least one other register being coupled in parallel between said first and said second registers; and wherein said control means includes means for enabling transfer of data between said first and said at least one other register, and means for preventing transfer of data between said first and said second registers.

Claim 16

The device of claim 12 wherein said subplurality of registers further includes a fourth register coupled in parallel to said first and said second registers.

Claim 17

The device of claim 13 wherein said control means further includes means for enabling transfer of data between said first and said fourth registers and means for enabling transfer of data between said second and said fourth registers.

Claim 18

The device of claim 12 further including an entry means coupled to said at least one other register for entering data therein.

Claim 19

The device of claim 12 wherein said at least one other register is coupled to said recirculating memory, and said control means includes means for enabling transfer of data from said recirculating memory directly to said at least one other register.

Claim 20

The device of claim 12 further including a display means coupled to said at least one other register for indicating the contents of said recirculating memory, and wherein said control means includes means for enabling said display means.

Claim 21

The device of claim 11 wherein said recirculating memory includes read means coupled to said arithmetic unit for serially reading said data into said arithmetic unit and write means coupled to said arithmetic unit for serially writing said data into said recirculating memory.

Claim 22

The device of claim 11 wherein said control means includes an adding means coupled to said subplurality of registers for combining selected portions of said data in said recirculating memory to form resultant data representing the algebraic sum of said selected portions.

Claim 23

In an electronic desk top calculator: an entry register having a plurality of digit order positions; digit entry means for entering numeric data into said entry register; means for shifting said data within said entry register to adjacent order positions, including means for generating a COUNTER INCREMENT signal for each shift of said data by one order position; means for enabling said shifting means; and a decimal point control system for decimal alignment of said data in said entry register to a predetermined decimal significance, said last-named means comprising: a decimal position signal generator for generating a DECIMAL NUMBER signal specifying the total desired number of decimal digit positions in said entry register; a counter coupled to said decimal position signal generator for controlling the total number of data shifts during decimal alignment; means for enabling said counter; said counter having an input coupled to said COUNTER INCREMENT signal generating means for incrementing said counter in response to the appearance of said COUNTER INCREMENT signal whenever said counter is enabled; said counter having an output coupled to said shifting means for disabling said shifting means when said counter reaches a predetermined state so that said data is shifted the required number of order positions to decimal align said data said total desired number of decimal digit positions.

Claim 24

In an electronic desk top calculator: an entry register having a plurality of digit order positions; digit entry means for entering numeric data into said entry register; means for shifting said data within said entry register to adjacent order positions, including means for generating a COUNTER INCREMENT signal for each shift of said data by one order position; means for enabling said shifting means; and a decimal point control system for decimal alignment of said data in said entry register to a predetermined decimal significance, said last-named means comprising: a decimal position signal generator for generating a DECIMAL NUMBER signal specifying the total desired number of decimal digit positions in said entry register; a counter coupled to said decimal position signal generator for controlling the total number of data shifts during decimal alignment; means for enabling said counter; said counter having an input coupled to said COUNTER INCREMENT signal generating means for incrementing said counter in response to the appearance of said COUNTER INCREMENT signal whenever said counter is enabled; said counter having an output coupled to said shifting means for disabling said shifting means when said counter reaches a predetermined state so that said data is shifted the required number of order positions to decimal align said data said total desired number of decimal digit positions.

Claim 25

The apparatus of claim 20 wherein said means for enabling said counter includes a plurality of entry gates coupled to said counter and said decimal position signal generator, and means for enabling said entry gates.

Claim 26

The apparatus of claim 21 wherein said means for enabling said entry gates includes at least one manually actuable function key.

Claim 27

The apparatus of claim 21 wherein said means for enabling said entry gates includes a decimal point circuit including a manually actuatable decimal point key for generating a DECIMAL POINT signal indIcating termination of entry of the whole number portion of said data, so that said counter is enabled whenever decimal digits are entered into said entry register.

Claim 28

The apparatus of claim 23 further including a decimal interlock circuit coupled to said counter and said decimal point circuit for generating a DECIMAL INTERLOCK signal for disabling said entry means whenever said counter reaches said predetermined state after said decimal point key has been actuated.

Claim 29

The apparatus of claim 20 wherein said means for enabling said counter includes means for setting said counter to the N''s complement of said desired number of digit positions specified by said decimal position signal generator, where N equals the total number of possible states of said counter.

Claim 30

The apparatus of claim 25 wherein N equals 16.

Claim 31

The apparatus of claim 20 wherein said counter is advanceable and said predetermined state comprises the zero state.