Immediate sequential access memory

Claim 1

IN A MEMORY DEVICE, A FIRST MEMORY ELEMENT HAVING AN INPUT AND A PLURALITY OF OUTPUTS, A SECOND MEMORY ELEMENT HAVING AN INPUT AND A PLURALITY OF OUTPUTS, INPUT MEANS FOR APPLYING INFORMATION TO THE INPUT OF THE FIRST MEMORY ELEMENT, FIRST SWITCH MEANS FOR SEQUENTIALLY APPLYING THE OUTPUTS OF THE FIRST MEMORY ELEMENT TO THE INPUT OF THE SECOND MEMORY ELEMENT, AN OUTPUT TERMINAL, SECOND SWITCH MEANS FOR SEQUENTIALLY APPLYING THE OUTPUTS OF THE SECOND MEMORY ELEMENT TO THE OUTPUT TERMINAL, FIRST COUNTER MEANS FOR CONTROLLING THE SEQUENTIAL OPERATION OF SAID FIRST SWITCH MEANS, SECOND COUNTER MEANS FOR CONTROLLING THE SEQUENTIAL OPERATION OF SAID SECOND SWITCH MEANS, CONTROL MEANS CONNECTED WITH SAID SECOND COUNTER MEANS FOR CONTROLLING THE FREQUENCY OF OPERATION OF THE SECOND COUNTER MEANS, MEANS CONNECTING THE SECOND MEANS TO SAID FIRST COUNTER MEANS TO CAUSE SAID FIRST COUNTER MEANS TO OPERATE AT A FREQUENCY WHICH IS A SUBMULTIPLE OF THE FREQUENCY OF OPERATION OF SAID SECOND COUNTER MEANS, AND MEANS FOR AFFECTING THE OPERATION OF SAID CONTROL MEANS TO INHIBIT THE OPERATION OF SAID SECOND COUNTER MEANS.