Data rate-changing and reordering circuits

Claim 1

Apparatus responsive to a single clock for processing an input sequence of n data signals, where n 2a and a is an integer, each of said signals occurring during a respective input interval, said apparatus comprising A. an ordered plurality of a stages, each comprising 1. an Input terminal and an output terminal, 2. a source of periodic control signals, 3. a plurality of transmission paths, each having a first and second terminal, and each interposing a different transmission delay, 4. gating means responsive to said control signals for diverting selected ones of signals applied at said input terminal to the first terminal of respective selected ones of said plurality of paths, said gating means comprising a plurality of paths, said gating means comprising a plurality of AND gates, each having a plurality of input leads and one output lead, first input means for applying signals in said input sequence to each of said AND gates, and second input means for applying said control signals to each of said AND gates, thereby to enable signals in said sequence to appear on selected ones of said output leads of said AND gates, 5. means interconnecting each of said second terminals and said output terminals, B. means for connecting the output terminal of each stage except the last to the input terminal of the immediately following stage, and C. means for applying said input sequence of signals at the input terminal of the first of said ordered stages, and wherein m is the integer ratio of the input rate of said input sequence to the rate of the processed sequence appearing at the output terminal of the ath of said stages, wherein said plurality of paths comprises two paths, and wherein at the ith stage, i 1,2,...,a, said delay in one of said two paths exceeds the delay in the other of said two paths by an amount equal to (m1)2a 1 input signal intervals.