Programmable clock having programmable delay and duty cycle based on a user-supplied reference clock

Claim 2

A circuit in an integrated circuit for selectively transforming an input clock signal, comprising: an internal oscillator that generates an internal clock signal; a first counter adapted to count each cycle of said internal clock signal and to generate an output signal corresponding thereto; a clock manipulation logic circuit adapted to receive the output signal produced by said first counter, and for producing a first transform value from the output signal and the input clock signal; and a second counter adapted to receive said first transform value from said clock manipulation logic circuit and for delaying generation of a clock circuit output signal until said second counter has counted to a value that is equal to said first transform value.

Claim 3

The circuit of claim 1, further comprising: a first register for temporarily storing said first counter output signal; and a second register for temporarily storing said second counter output signal.

Claim 4

The circuit of claim 1, wherein a duty cycle of said input clock signal is transformed by said clock manipulation logic circuit.

Claim 5

The circuit of claim 1, wherein said input clock signal is delayed by said clock manipulation logic circuit.

Claim 6

The circuit of claim 1, wherein said input clock signal is multiplied by said clock manipulation logic circuit.

Claim 7

The circuit of claim 1, wherein said input clock signal is divided by said clock manipulation logic circuit.

Claim 8

The circuit of claim 1, wherein said internal clock further comprises an oscillator circuit.

Claim 9

The circuit of claim 7, wherein said oscillator has a period of about 0.5 nsec.

Claim 10

The circuit of claim 1, further comprising: a third counter adapted to receive a second transform value from said clock manipulation logic circuit and for maintaining said clock circuit output signal in one of a high state or low state until said third counter has counted to a value that is equal to said second transform value.

Claim 11

A circuit in an integrated circuit for selectively transforming an input clock signal, comprising: an internal oscillator that generates an internal clock signal; a first counter adapted to count each cycle of said internal clock signal and to generate an output signal corresponding thereto; a clock manipulation logic circuit adapted to receive the output signal produced by said first counter, and for producing a first transform value from the output signal and the input clock signal; and a second counter adapted to receive a first transform value from said clock manipulation logic circuit and for maintaining said clock circuit output signal in one of a high state or low state until said second counter has counted to a value that is equal to said first transform value.

Claim 12

A circuit in an integrated circuit for selectively transforming an input clock signal, comprising: an internal oscillator that generates an internal clock signal; a first counter adapted to count each cycle of said internal clock signal and to generate an output signal corresponding thereto; a clock manipulation logic circuit adapted to receive the output signal produced by said first counter, and for producing a first transform value from the output signal and the input clock signal; and a second counter adapted to receive a first transform value from said clock manipulation logic circuit and for maintaining said clock circuit output signal in one of a high state or low state until said second counter has counted to a value that is equal to said first transform value.

Claim 13

The circuit of claim 10, wherein a duty cycle of said input clock signal is transformed by said clock manipulation logic circuit.

Claim 14

The circuit of claim 10, wherein said input clock signal is delayed by said clock manipulation logic circuit.

Claim 15

The circuit of claim 10, wherein said input clock signal is multiplied by said clock manipulation logic circuit.

Claim 16

The circuit of claim 10, wherein said input clock signal is divided by said clock manipulation logic circuit.

Claim 17

The circuit of claim 10, wherein said internal clock further comprises an oscillator circuit.

Claim 18

The circuit of claim 15, wherein said oscillator has a period of about 0.5 nsec.

Claim 19

The circuit of claim 10, further comprising: a third counter adapted to receive a second transform value from said clock manipulation logic circuit and for delaying generation of a clock circuit output signal until said third counter has counted to a value that is equal to said second transform value.

Claim 20

A circuit for selectively transforming an input clock signal, comprising: an internal clock that operates at a rate which is fast with respect to the rate of said input clock signal, said internal clock generating an internal clock signal; a first up counter adapted to count each cycle of said internal clock signal that is generated during each input clock cycle and to generate an output signal corresponding thereto; a first register for temporarily storing said first up counter output signal; a second up counter adapted to count each cycle of said internal clock signal that is generated during each input clock cycle only while said input clock is in one of a high or low state and to generate an output signal corresponding thereto; a second register for temporarily storing said second up counter output signal; a clock manipulation logic circuit adapted to receive the output signals produced by said first and second up counters from said first and second registers during each input clock cycle, and for producing an input clock signal transform therefrom; a first down counter adapted to receive a first transform value from said clock manipulation logic circuit and for delaying generation of a clock circuit output signal until said first down counter has counted down to zero; and a second down counter adapted to receive a second transform value from said clock manipulation logic circuit and for maintaining said clock circuit output signal in one of a high state or low state until said second down counter has counted down to zero.

Claim 21

A circuit for selectively transforming an input clock signal, comprising: an internal clock that operates at a rate which is fast with respect to the rate of said input clock signal, said internal clock generating an internal clock signal; a first up counter adapted to count each cycle of said internal clock signal that is generated during each input clock cycle and to generate an output signal corresponding thereto; a first register for temporarily storing said first up counter output signal; a second up counter adapted to count each cycle of said internal clock signal that is generated during each input clock cycle only while said input clock is in one of a high or low state and to generate an output signal corresponding thereto; a second register for temporarily storing said second up counter output signal; a clock manipulation logic circuit adapted to receive the output signals produced by said first and second up counters from said first and second registers during each input clock cycle, and for producing an input clock signal transform therefrom; a first down counter adapted to receive a first transform value from said clock manipulation logic circuit and for delaying generation of a clock circuit output signal until said first down counter has counted down to zero; and a second down counter adapted to receive a second transform value from said clock manipulation logic circuit and for maintaining said clock circuit output signal in one of a high state or low state until said second down counter has counted down to zero.

Claim 22

The circuit of claim 18, further comprising: an input logic circuit adapted to receive said input clock signal, said input logic circuit producing a CLK1 signal therefrom, said CLK1 signal operable to enable said second up counter; and said input logic circuit producing a CLKBEG signal therefrom, said CLKBEG signal operable to reset said first and second up counters, and to load said first transform value to said first down counter from said clock manipulation logic circuit.

Claim 23

The circuit of claim 18, further comprising: an output logic circuit adapted to receive a DZERO signal from said first down counter, said DZERO signal operable to enable said first down counter; and for generating a LDCNTH from said DZERO signal, said LDCNTH signal operable load said second transform value to said second down counter from said clock manipulation logic circuit.

Claim 24

The circuit of claim 18, wherein said clock manipulation logic circuit is adapted to selectively perform any of the following input clock signal transforms: input clock signal duty cycle adjustment, input clock signal delay, input clock signal advance, input clock signal multiplication, and input clock signal division.

Claim 25

The circuit of claim 18, wherein said internal clock further comprises an oscillator circuit.

Claim 26

The circuit of claim 22, wherein said oscillator has a period of about 0.5 nsec.

Claim 29

The method of claim 24, wherein said input clock signal duty cycle is transformed during said producing step.

Claim 30

The method of claim 24, wherein said input clock signal is delayed during said producing step.

Claim 31

The method of claim 24, wherein said input clock signal is multiplied during said producing step.