EP0266065A2
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EP
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Programmable sequence generator
Assignee: Texas Instruments Inc
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Filing: 1987-09-29
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Granted: —
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Expires: 2007-09-29
Abstract
Abstract A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of he logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.
Inventors
- 👤 Robert K. Breuninger
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 10:12
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
85 words
A programmable sequence generator comprising: a programmable combinatorial logic matrix having a plurality of external and internal inputs and a plurality of outputs; a counter having as outputs a plurality of count lines coupled as internal inputs to said logic matrix; said logic matrix operable to be programmed with at least one logic equation defining the state of an output of said matrix, said equation including among its variables the states of selected ones of said external inputs and selected ones of said count lines.
Claim 2
Dependent Claim
85 words
A programmable sequence generator comprising: a programmable combinatorial logic matrix having a plurality of external and internal inputs and a plurality of outputs; a counter having as outputs a plurality of count lines coupled as internal inputs to said logic matrix; said logic matrix operable to be programmed with at least one logic equation defining the state of an output of said matrix, said equation including among its variables the states of selected ones of said external inputs and selected ones of said count lines.
Claim 3
Dependent Claim
58 words
The programmable sequence generator of Claim 1, and further comprising at least one state register having at least one input coupled to an output of said matrix, an output of said state register coupled as an input to said matrix, such that a stored state can be used as a variable in said at least one logic equation.
Claim 4
Dependent Claim
48 words
The progammable sequence generator of Claim 2, wherein a clock source triggers the operation of said counter and said at least one state register, an architectural fuse associated with said clock source for selecting between a trigger on a descending transition or a trigger on an ascending transition.
Claim 5
Dependent Claim
50 words
The programmable sequence generator of Claim 1, wherein said combinatorial logic matrix comprises a programmable product matrix coupled to said logic matrix inputs, a programmable sum matrix, said product matrix having outputs coupled to inputs of said sum matrix, outputs of said sum matrix coupled to said logic matrix outputs.
Claim 6
Dependent Claim
26 words
The programmable sequence generator of Claim 1, wherein said at least one logic equation defines a timing sequence produced at least one of said matrix outputs.
Claim 7
Dependent Claim
26 words
The programmable sequence generator of Claim 5, wherein said timing sequence is programmed to repeat within a preselected number of counts as counted by said counter.
Claim 8
Dependent Claim
51 words
The programmable sequence generator of Claim 1, wherein said matrix outputs are each coupled to an output storage register and further connected directly to said matrix, a multiplexer connected to a respective matrix output line and an output from said register, said multiplexer programmable to select between registered and nonregistered output.
Claim 9
Dependent Claim
137 words
A programmable sequence generator according to Claim 1, wherein said combinatorial logic matrix includes a programmable product matrix coupled to said logic matrix inputs, a programmable sum matrix having a plurality of inputs, said product matrix having outputs coupled to inputs of said sum matrix, outputs of said sum matrix coupled to said logic matrix outputs, said programmable product matrix having a plurality of inputs, and including a counter having a plurality of count lines selectively connected to said product matrix, said product matrix having a plurality of product outputs selectively coupled to said inputs of said sum matrix, said sum matrix having a plurality of sum outputs, each sum output programmable to provide a value equal to the value of at least one selected combinatorial logic function of said product matrix inputs and said count lines.
Claim 10
Dependent Claim
106 words
The programmable sequence generator of Claim 8, further comprising: a counter input of said counter for resetting said counter to zero, at least one of said sum outputs coupled to said counter input for enabling a clear signal on said at least one sum output for resetting said counter, at least one input to said sum matrix coupled to an output of a counter product gate, said counter product gate having a plurality of inputs connected to selected ones of said count lines, a preselected count on said count lines causing said counter product gate to transmit a signal to said at least one sum output.
Claim 11
Dependent Claim
66 words
The programmable sequence generator of Claim 8, and further comprising at least one state register having at least one input coupled to an output of said sum matrix, said state register having at least one output coupled to a selected input of said product matrix, such that at least one state stored in said state register is used as a variable in said combinatorial logic function.
Claim 12
Dependent Claim
68 words
The programmable sequence generator of Claim 10, wherein said product matrix is programmable to form circuitry embodying a maximum count product term that has a selected value when said counter has reached its count capacity; a maximum count sum term programmed in said sum matrix using said maximum count product term; said state register coupled to said maximum count sum term for storing a most significant counting bit.
Claim 13
Dependent Claim
52 words
The programmable sequence generator of Claim 11, wherein a complement of said state register output is used in forming said maximum count product term, said selected value having a selected polarity, said maximum count product term having said selected value only when said complement has the same polarity as said selected value.
Claim 14
Dependent Claim
120 words
The programmable sequence generator of Claim 11 wherein said count lines and state register output are used to form circuitry embodying a second maximum count product term, said counter having a maximum count capacity, said second maximum count product term having a second selected value when said count lines represent a number equal to said maximum count capacity and when said state register output is of a same polarity as said second maximum count product term, said second maximum count product term used in forming a second maximum count sum term coupled to said state register, said second maximum count sum term, upon the attainment of a selected state, causing said state register to change the polarity of its output.
Claim 15
Dependent Claim
65 words
The programmable sequence generator of Claim 11, wherein said logic matrix outputs each further include a three-state amplifier having an input and an output, said amplifier input connected to an output of said output register, a high-impedance line connected to a gate having an architectural fuse, a high impedance state on each said amplifier output selectable by said gate when said architectural fuse is blown.
Claim 16
Dependent Claim
56 words
The programmable sequence generator of Claim 8, wherein each of a plurality of said sum outputs are coupled to a respective output register and a respective nonregistered output line, a multiplexer coupled to an output of said respective output register and said respective nonregistered output line, said multiplexer programmable for selecting between registered and nonregistered output.
Claim 17
Dependent Claim
51 words
The programmable sequence generator of Claim 8, and further comprising a clock source for synchronous operation of said counter, said clock source including an architectural fuses and a clock signal input, said source selectable to trigger either on a positive-going transition or on a negative-going transition of an input clock signal.
Claim 18
Dependent Claim
72 words
The programmable sequence generator of Claim 8, wherein said counter has a countlhold input, one state of said count/hold input causing the counter to stop counting, another state thereof causing said counter to resume counting; said countlhold input coupled to an output of said sum matrix, such that a predetermined combinatorial function programmed into said product matrix and said sum matrix will cause a selected signal to appear at said count/hold input.
Claim 19
Independent Claim
174 words
A method for programming a sequence generator for generating a plurality of predetermined clock sequences, the clock sequences each having a plurality of transitions at predetermined intervals, the sequence generator including a combinatorial logic matrix having a plurality of inputs and outputs, a counter coupled to inputs of the logic matrix, the method comprising: programming at least one count clock cycle into the logic matrix for defining when the clock sequences will repeat; referring each transition of the clock sequences to a count in the count clock cycle; forming a product term for each referred count as a function of the count; programming a product term circuit in the matrix for each product term using selected ones of the count lines; programming logic functions of selected ones of the matrix inputs and the count lines by selectively suing the product term circuits in forming a plurality of sum term circuits, one sum term circuit for each clock sequence; and - outputting the clock sequences by coupling the sum term circuits to respective matrix outputs.
Claim 20
Independent Claim
174 words
A method for programming a sequence generator for generating a plurality of predetermined clock sequences, the clock sequences each having a plurality of transitions at predetermined intervals, the sequence generator including a combinatorial logic matrix having a plurality of inputs and outputs, a counter coupled to inputs of the logic matrix, the method comprising: programming at least one count clock cycle into the logic matrix for defining when the clock sequences will repeat; referring each transition of the clock sequences to a count in the count clock cycle; forming a product term for each referred count as a function of the count; programming a product term circuit in the matrix for each product term using selected ones of the count lines; programming logic functions of selected ones of the matrix inputs and the count lines by selectively suing the product term circuits in forming a plurality of sum term circuits, one sum term circuit for each clock sequence; and - outputting the clock sequences by coupling the sum term circuits to respective matrix outputs.
Claim 21
Dependent Claim
66 words
The method of Claim 18, and further including the steps of selectively connecting a plurality of count output lines from the counter to form at least one count product term circuit in a product matrix of said logic matrix; and coupling said count product term circuit to the counter such that a selected value of the count product term circuit will reset the counter to zero.
Claim 22
Dependent Claim
29 words
The method of Claim 18, and further including the steps of selecting for a clock source clocking the counter to trigger on either a positive or a negative transition.
Claim 23
Dependent Claim
43 words
The method of Claim 18, and further including the step of selecting for registered output of at least one matrix output, such that a product term circuit need be programmed only for each transition of the clock sequence appearing at the matrix output.
Claim 24
Dependent Claim
66 words
The method of Claim 18, and further including the steps of: connecting inputs of at least one state register of the programmable sequence generator to selected outputs of the logic matrix; storing a state generated by at least one logic function programmed into the logic matrix in the state register; and using the stored state as a variable in other logic functions programmed into the matrix.
Claim 25
Dependent Claim
114 words
The method of Claim 22, and further including the steps of: associating each of a plurality of states with a selected count cycle; storing at least one of said states in a plurality of state registers: causing the counter to count according to the count cycle associated with the stored state; activating selected programmed combinatorial functions referenced to the associated count cycle to control selected outputs of the logic matrix; storing a second state in said state register; causing the counter to count according to a second count cycle associated with the second state; and activating selected programmed combinatorial functions referenced to the second count cycle to control selected outputs of the logic matrix.
Claim 26
Dependent Claim
158 words
The method of Claim 22, and further including the steps of programming a first count cycle product term circuit into the logic matrix, such that the first count cycle product term circuit is active upon the counter reaching its maximum capacity, coupling the first count cycle product term circuit to an input of the state register; connecting an output of the state register to a selected input in the matrix using the selected input in forming a second count cycle product term circuit in the matrix, the second count cycle product term circuit active upon the selected input taking a predetermined value and the counter reaching its maximum capacity; using the second count cycle product term circuit in forming to a clear line sum term circuit; and coupling the clear line sum term circuit to an input of the counter for clearing the counter, such that the state register increases the capacity of the counter by one stage.
Claim 27
Dependent Claim
99 words
The method of Claim 18,and further including the steps of using at least one external input in forming a product term circuit programmed in a product matrix of the logic matrix; forming a count/hold sum term circuit in a sum matrix of the logic matrix, using the product term circuit; coupling the count/hold sum term circuit to a count/hold input of the counter; causing the counter to pause in counting by forcing the count/hold sum term circuit to a first value; and causing said counter to resume counting by forcing the count/hold sum term circuit to a second value.
Claim 28
Dependent Claim
21 words
The method of Claim 18, wherein the combinatorial logic matrix comprises and AND matrix having outputs connected to an OR matrix.
References Cited (Backward Citations)
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