Logic array having high frequency internal clocking

Claim 2

A state machine structure comprising: logic array means having input leads and output leads; at least one register means having input terminals coupled to said output leads of said logic array means and having output terminals coupled to said input leads of said logic array means; and clock generating means for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means; wherein said clock generating means incorporates a phase-locked loop having first and second inputs, and having said reference signal coupled to said first input of said phase-locked loop, and an output terminal of said register means coupled to said second input of said phase-locked loop.

Claim 3

The structure of claim 1 wherein said structure is a monolithic structure.

Claim 4

The structure of claim 2 wherein said coupling between said output terminal of said register means and said second input of said phase-locked lop is accomplished through a connection external to said monolithic structure.

Claim 5

The structure of claim 2 wherein said logic array means comprises an AND array means having input leads and output leads, an OR array means having input leads coupled to said output leads of said AND array means and having output leads, said register means having input terminals coupled to said output leads of said AND array means, but not coupled to said output leads of said OR array, and having output terminals coupled to said input leads of said AND array means.

Claim 6

The structure of claim 2 wherein said coupling between said output terminal of said register means and said second input of said phase-locked loop is accomplished through a connection internal to said monolithic structure.

Claim 7

The structure of claim 2 wherein said reference signal is an externally generated clock signal.

Claim 8

The structure of claim 2 wherein said logic array means comprises: AND array means for performing functional AND operations having input leads and output leads; and OR array means for performing functional OR operations having input leads coupled to said output leads of said AND array means and having output leads.

Claim 9

The structure of claim 7 wherein said AND array means is programmable.

Claim 10

The structure of claim 7 wherein at least one of said register means comprises output register means having input terminals coupled to said output leads of said OR array means and having output terminals coupled to output leads of said structure.

Claim 11

The structure of claim 9 wherein at least one other of said register means comprises buried register means having input terminals coupled to one or more of said output leads of said logic array means and having output terminals coupled to one or more input terminals of said logic array means, and wherein said output of said clock generating means is coupled to clock input terminals of one or more of said buried register means.

Claim 12

The structure of claim 10 wherein said buried register means and said output register means comprise flip flops.

Claim 13

The structure of claim 7 further including an end count register having an input terminal coupled to an output of said AND array and an output terminal connected to an input of said AND array.

Claim 14

The structure of claim 7 wherein external outputs are coupled to said state machine through respective input latches, and wherein said input latches are enabled at a rate different than the rate of said clock signal generated by said clock generating means.

Claim 15

A monolithic structure comprising: a state machine having one or more input terminals and a plurality of output terminals; at least one register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals; and a phase-locked loop clock generating means to supply a feedback signal for comparison with a reference signal; one of said output terminals of said register means coupled to an input of said phase-locked loop clock generating means, said register means having an associated clock input terminal coupled to an output of said phase-locked loop clock generating means.

Claim 16

A monolithic structure comprising: a state machine having one or more input terminals and a plurality of output terminals; at least one register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals; and a phase-locked loop clock generating means to supply a feedback signal for comparison with a reference signal; one of said output terminals of said register means coupled to an input of said phase-locked loop clock generating means, said register means having an associated clock input terminal coupled to an output of said phase-locked loop clock generating means.

Claim 17

A circuit comprising: a clock generating means having one or more input leads and one or more output leads, at least one of said input leads being coupled for receiving an externally generated periodic reference signal, and outputting one or more clock signals on said output leads; and an output means having one or more input leads coupled to at least one of said output leads of said clock generating means and outputting a plurality of individually controllable signals on one or more output leads of said output means which transition at a time referenced to transitions of said reference signal regardless of any internal propagation delays of said circuit; wherein said plurality of individually controllable signals are phase-aligned or selectively phase-shifted with said externally generated periodic reference signal.

Claim 18

A circuit comprising: a clock generating means having one or more input leads and one or more output leads, at least one of said input leads being coupled for receiving an externally generated periodic reference signal, and outputting one or more clock signals on said output leads; and an output means having one or more input leads coupled to at least one of said output leads of said clock generating means and outputting a plurality of individually controllable signals on one or more output leads of said output means which transition at a time referenced to transitions of said reference signal regardless of any internal propagation delays of said circuit; wherein said plurality of individually controllable signals are phase-aligned or selectively phase-shifted with said externally generated periodic reference signal.

Claim 19

A circuit whose output signals are made to transition at a time reference to a time of transition of an externally generated reference signal applied to said circuit regardless of any internal propagation delays of said circuit, said circuit comprising: means for receiving an externally generated periodic reference signal and a feedback signal and for providing an output clock signal at a frequency different than said reference signal; logic array means for receiving input signals and for performing logical functions on said input signals and for providing results of said logical functions at output terminals of said logic array means; and one or more register means, at least one of said register means having one or more input terminals coupled to said output terminals of said logic array means and having one or more output terminals coupled to inputs of said logic array means, at least one of said register means including an output terminal for providing said feedback signal, and at least one of said register means having a clock input terminal coupled to receive said output clock signal.

Claim 20

A circuit whose output signals are made to transition at a time reference to a time of transition of an externally generated reference signal applied to said circuit regardless of any internal propagation delays of said circuit, said circuit comprising: means for receiving an externally generated periodic reference signal and a feedback signal and for providing an output clock signal at a frequency different than said reference signal; logic array means for receiving input signals and for performing logical functions on said input signals and for providing results of said logical functions at output terminals of said logic array means; and one or more register means, at least one of said register means having one or more input terminals coupled to said output terminals of said logic array means and having one or more output terminals coupled to inputs of said logic array means, at least one of said register means including an output terminal for providing said feedback signal, and at least one of said register means having a clock input terminal coupled to receive said output clock signal.

Claim 21

The circuit of claim 16 wherein said means for receiving incorporates a phase-locked loop having a first and a second input, and having said reference signal coupled to said first input, and an output terminal of one of said register means coupled to said second input of said phase-locked loop.

Claim 22

The structure of claim 17 wherein said structure is a monolithic structure.

Claim 23

The structure of claim 18 wherein said coupling between said output terminal of one of said register means and said second input of said phase-locked loop is accomplished through a connection external to said monolithic structure.

Claim 24

The structure of claim 18 wherein said coupling between said output terminal of one of said register means and said second input of said phase-locked loop is accomplished through a connection internal to said monolithic structure.

Claim 25

The structure of claim 18 wherein said logic array means comprises: AND array means for performing functional AND operations having input leads and output leads; and OR array means for performing functional OR operations having input leads coupled to said output leads of said AND array means and having output leads.

Claim 26

The structure of claim 21 wherein said AND array means is programmable.

Claim 27

The structure of claim 21 wherein at least one of said register means comprises output register means having input terminals coupled to said output leads of said OR array means.

Claim 28

The structure of claim 23 further comprising one or more buried register means having input terminals coupled to said output terminals of said logic array means and having output terminals coupled to input terminals of said logic array means, and wherein said output of said clock generating means is coupled to clock input terminals of one or more of said buried register means.

Claim 29

A monolithic structure comprising: a state machine having one or more input terminals and a plurality of output terminals; at least one register means, at least one of said register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals; and clock generating means incorporating a phase-locked loop for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means, one of said output terminals of said register means being coupled to an input of said clock generating means for supplying a feedback signal to be compared with said reference signal.

Claim 30

A monolithic structure comprising: a state machine having one or more input terminals and a plurality of output terminals; at least one register means, at least one of said register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals; and clock generating means incorporating a phase-locked loop for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means, one of said output terminals of said register means being coupled to an input of said clock generating means for supplying a feedback signal to be compared with said reference signal.

Claim 31

The structure of claim 25 wherein said reference signal is an externally generated clock signal.

Claim 32

The structure of claim 25 wherein said state machine comprises: AND array means for performing functional AND operations having input leads and output leads; and OR array means for performing functional OR operations having input leads coupled to said output leads of said AND array means and having output leads.

Claim 33

The structure of claim 27 wherein said AND array means is programmable.

Claim 34

The structure of claim 27 wherein at least one of said register means comprises output register means having input terminals coupled to said output leads of said OR array means.