US6483359B2 — Delay locked loop for use in semiconductor memory…

Claim 1

Independent Claim 113 words

A delay locked loop (DLL) comprising: a first shift register responsive to a first shift-right signal and a first shift-left signal; a first delay line for delaying an internal clock in response to an output of the first shift register, wherein the first delay line includes a plurality of first delay units; a second shift register responsive to at least one of a second shift-right signal and a second shift-left signal outputted from the first shift register; and a second delay line for delaying an output of the first delay line in response to an output of the second shift register, wherein the second delay line includes a plurality of second delay units.

Claim 2

Dependent Claim 113 words

A delay locked loop (DLL) comprising: a first shift register responsive to a first shift-right signal and a first shift-left signal; a first delay line for delaying an internal clock in response to an output of the first shift register, wherein the first delay line includes a plurality of first delay units; a second shift register responsive to at least one of a second shift-right signal and a second shift-left signal outputted from the first shift register; and a second delay line for delaying an output of the first delay line in response to an output of the second shift register, wherein the second delay line includes a plurality of second delay units.

Claim 3

Dependent Claim 86 words

The delay locked loop as recited in claim 1 further comprising: a clock buffer for receiving an external clock to generate the internal clock; a delay monitor for receiving an output of the second delay line to add a predetermined amount of delay to an output of the delay locked loop; and a phase detector for comparing a phase difference between the internal clock and the output of the delay monitor, the phase detector generating one of the first shift-left signal and the first shift-right signal.

Claim 4

Dependent Claim 36 words

The delay locked loop as recited in claim 1 , wherein the first delay line includes: a first inverter for inverting the internal clock; and a second inverter for inverting an output of the first inverter.

Claim 5

Dependent Claim 44 words

The delay locked loop as recited in claim 3 , wherein each of the plurality of first delay units includes: a transistor having a gate for receiving a control signal outputted from the first shift register; and a capacitor in communication with the transistor.

Claim 6

Dependent Claim 90 words

The delay locked loop as recited in claim 3 , wherein the second delay line includes a plurality of first NAND gates, each first NAND gate receiving an output of the first delay line and an output of the second shift register, and wherein each of the second delay units includes: (1) a second NAND gate receiving an output of a respective one of the first NAND gates and (2) a third NAND gate receiving an output of the second NAND gate, the second delay units being connected in series.

Claim 7

Dependent Claim 59 words

The delay locked loop as recited in claim 1 , wherein each of the first delay units is adapted to delay the internal clock by a first delay amount, each of the second delay units is adapted to delay the internal clock by a second delay amount, and the second delay amount is greater than the first delay amount.

Claim 8

Dependent Claim 24 words

The delay locked loop as recited in claim 6 , wherein the second delay amount is an integer multiple of the first delay amount.

Claim 9

Dependent Claim 37 words

The delay locked loop as recited in claim 7 , wherein a total delay produced by activating all of the first delay units in the plurality of first delay units is less than the second delay amount.

Claim 10

Dependent Claim 38 words

The delay locked loop as recited in claim 1 , wherein the second shift-right signal is produced when all of the first delay units are activated and a first shift-right signal is received at the first shift register.

Claim 11

Dependent Claim 39 words

The delay locked loop as recited in claim 9 , wherein the first delay units are all deactivated when a first shift-right signal is received at the first shift register when all of the first delay units are activated.

Claim 12

Dependent Claim 38 words

The delay locked loop as recited in claim 9 , wherein the second shift-left signal is produced when none of the first delay units are activated and a first shift-left signal is received at the first shift register.

Claim 13

Dependent Claim 39 words

The delay locked loop as recited in claim 11 , wherein the first delay units are all activated when a first shift-left signal is received at the first shift register when none of the first delay units are activated.

Claim 14

Dependent Claim 25 words

The delay locked loop as recited in claim 6 , wherein a first shift-right signal results in a delay increase of the first delay amount.

Claim 15

Dependent Claim 25 words

The delay locked loop as recited in claim 7 , wherein a first shift-left signal results in a delay decrease of the first delay amount.

Claim 16

Dependent Claim 31 words

The delay locked loop as recited in claim 1 , wherein a second delay unit is activated if all of the first delay units are activated and more delay is needed.

Claim 17

Dependent Claim 96 words

For use in a semiconductor memory, a delay locked loop comprising: a first delay line for selectively delaying a received signal to develop a delayed signal, the first delay line having a plurality of delay units, at least one of the delay units comprising a capacitor and a controlled switch, the controlled switch being switchable between a first state wherein the capacitor is connected to delay the received signal and a second state wherein the capacitor is disconnected; and a second delay line in communication with the first delay line for selectively delaying the delayed signal.

Claim 18

Dependent Claim 96 words

For use in a semiconductor memory, a delay locked loop comprising: a first delay line for selectively delaying a received signal to develop a delayed signal, the first delay line having a plurality of delay units, at least one of the delay units comprising a capacitor and a controlled switch, the controlled switch being switchable between a first state wherein the capacitor is connected to delay the received signal and a second state wherein the capacitor is disconnected; and a second delay line in communication with the first delay line for selectively delaying the delayed signal.

Claim 19

Dependent Claim 22 words

The delay locked loop as recited in claim 16 , wherein the delayed signal is not delayed relative to the received signal.

Claim 20

Dependent Claim 19 words

The delay locked loop as recited in claim 16 , wherein the received signal comprises an internal clock signal.

Claim 21

Dependent Claim 36 words

The delay locked loop as recited in claim 16 , wherein the first delay line comprises: a first inverter for inverting the received signal; and a second inverter for inverting an output of the first inverter.

Claim 22

Dependent Claim 17 words

The delay locked loop as recited in claim 16 , wherein the controlled switch comprises a transistor.

Claim 23

Dependent Claim 34 words

The delay locked loop as recited in claim 16 , wherein the second delay line comprises: a plurality of second delay line NAND gates; and a plurality of second delay units connected in series.

Claim 24

Dependent Claim 50 words

The delay locked loop as recited in claim 21 , wherein each of the second delay units comprises: a first NAND gate receiving an output of a corresponding one of the second delay line NAND gates; and a second NAND gate for receiving an output of the first NAND gate.

Claim 25

Dependent Claim 48 words

The delay locked loop as recited in claim 21 , wherein each of the second delay units comprises: a first NAND gate receiving an output of a corresponding one of the second delay line NAND gates; and an inverter for inverting an output of the first NAND gate.

Claim 26

Dependent Claim 84 words

The delay locked loop as recited in claim 16 further comprising: a first shift register in communication with the first delay line; and a second shift register in communication with the second delay line, wherein the first shift register triggers a first shift-right signal in response to a first predetermined condition and triggers a first shift-left signal in response to a second predetermined condition, and wherein the second shift register is responsive to at least one of the shift-right signal and the shift-left signal.

Claim 27

Dependent Claim 29 words

The delay locked loop as recited in claim 24 further comprising: a phase comparator coupled to the first shift register; and a delay monitor coupled to the phase comparator.

Claim 28

Dependent Claim 74 words

The delay locked loop as recited in claim 16 , wherein each of the delay units in the first delay line is adapted to delay the received signal by a first delay amount, the second delay line includes a plurality of second delay units, each of the second delay units is adapted to delay the delayed signal by a second delay amount, and the second delay amount is greater than the first delay amount.

Claim 29

Dependent Claim 24 words

The delay locked loop as recited in claim 26 , wherein the second delay amount is an integer multiple of the first delay amount.

Claim 30

Dependent Claim 40 words

The delay locked loop as recited in claim 27 , wherein a total delay produced by activating all of the delay units in the plurality of delay units in the first delay line is less than the second delay amount.

Claim 31

Dependent Claim 74 words

The delay locked loop as recited in claim 24 , wherein each of the delay units in the first delay line is adapted to delay the received signal by a first delay amount, the second delay line includes a plurality of second delay units, each of the second delay units is adapted to delay the delayed signal by a second delay amount, and the second delay amount is greater than the first delay amount.

Claim 32

Dependent Claim 42 words

The delay locked loop as recited in claim 25 , wherein the first shift-right signal is produced when all of the delay units in the first delay line are activated and a second shift-right signal is received at the first shift register.

Claim 33

Dependent Claim 42 words

The delay locked loop as recited in claim 30 , wherein the delay units in the first delay line are all deactivated when the second shift-right signal is received at the first shift register when all of the delay units are activated.

Claim 34

Dependent Claim 42 words

The delay locked loop as recited in claim 30 , wherein the first shift-left signal is produced when none of the delay units in the first delay line are activated and a second shift-left signal is received at the first shift register.

Claim 35

Dependent Claim 47 words

The delay locked loop as recited in claim 32 , wherein the delay units in the first delay line are all activated when the second shift-left signal is received at the first shift register when none of the delay units in the first delay line are activated.

Claim 36

Dependent Claim 25 words

The delay locked loop as recited in claim 26 , wherein a first shift-right signal results in a delay increase of the first delay amount.

Claim 37

Dependent Claim 25 words

The delay locked loop as recited in claim 34 , wherein a first shift-left signal results in a delay decrease of the first delay amount.

Claim 38

Dependent Claim 47 words

The delay locked loop as recited in claim 16 , wherein the second delay line includes a plurality of second delay units, and a second delay unit is activated if all of the delay units in the first delay line are activated and more delay is needed.

Claim 39

Dependent Claim 115 words

For use in a semiconductor memory, a delay locked loop comprising: a first delay line for selectively delaying a received signal to develop a delayed signal, the first delay line having a plurality of first delay units, each of the first delay units being adapted to selectively delay the received signal by a first delay amount; and a second delay line in communication with the first delay line for selectively delaying the delayed signal, the second delay line having a plurality of second delay units, each of the second delay units being adapted to selectively delay the received signal by a second delay amount, the second delay amount being larger than the first delay amount.

Claim 40

Dependent Claim 115 words

For use in a semiconductor memory, a delay locked loop comprising: a first delay line for selectively delaying a received signal to develop a delayed signal, the first delay line having a plurality of first delay units, each of the first delay units being adapted to selectively delay the received signal by a first delay amount; and a second delay line in communication with the first delay line for selectively delaying the delayed signal, the second delay line having a plurality of second delay units, each of the second delay units being adapted to selectively delay the received signal by a second delay amount, the second delay amount being larger than the first delay amount.

Claim 41

Dependent Claim 22 words

The delay locked loop as recited in claim 37 , wherein the delayed signal is not delayed relative to the received signal.

Claim 42

Dependent Claim 19 words

The delay locked loop as recited in claim 37 , wherein the received signal comprises an internal clock signal.

Claim 43

Dependent Claim 36 words

The delay locked loop as recited in claim 37 , wherein the first delay line comprises: a first inverter for inverting the received signal; and a second inverter for inverting an output of the first inverter.

Claim 44

Dependent Claim 34 words

The delay locked loop as recited in claim 37 , wherein at least one of the plurality of first delay units includes: a controlled switch; and a capacitor in communication with the controlled switch.

Claim 45

Dependent Claim 17 words

The delay locked loop as recited in claim 41 , wherein the controlled switch comprises a transistor.

Claim 46

Dependent Claim 49 words

The delay locked loop as recited in claim 37 , wherein the second delay line further comprises: a plurality of second delay line NAND gates, each of the second delay line NAND gates being in communication with a corresponding one of the second delay units; and an output unit.

Claim 47

Dependent Claim 41 words

The delay locked loop as recited in claim 37 , wherein each of the second delay units comprises: a first logic element for delaying a received signal; and a second logic element for delaying an output of the first logic element.

Claim 48

Dependent Claim 84 words

The delay locked loop as recited in claim 37 further comprising: a first shift register in communication with the first delay line; and a second shift register in communication with the second delay line, wherein the first shift register triggers a first shift-right signal in response to a first predetermined condition and triggers a first shift-left signal in response to a second predetermined condition, and wherein the second shift register is responsive to at least one of the shift-right signal and the shift-left signal.

Claim 49

Dependent Claim 29 words

The delay locked loop as recited in claim 45 further comprising: a phase comparator coupled to the first shift register; and a delay monitor coupled to the phase comparator.

Claim 50

Dependent Claim 24 words

The delay locked loop as recited in claim 37 , wherein the second delay amount is an integer multiple of the first delay amount.

Claim 51

Dependent Claim 30 words

The delay locked loop as recited in claim 47 , wherein a total delay produced by activating all of the first delay units is less than the second delay amount.

Claim 52

Dependent Claim 38 words

The delay locked loop as recited in claim 45 , wherein the first shift-right signal is produced when all of the first delay units are activated and a second shift-right signal is received at the first shift register.

Claim 53

Dependent Claim 39 words

The delay locked loop as recited in claim 49 , wherein the first delay units are all deactivated when the second shift-right signal is received at the first shift register when all of the first delay units are activated.

Claim 54

Dependent Claim 38 words

The delay locked loop as recited in claim 45 , wherein the first shift-left signal is produced when none of the first delay units are activated and a second shift-left signal is received at the first shift register.

Claim 55

Dependent Claim 39 words

The delay locked loop as recited in claim 51 , wherein the first delay units are all activated when the second shift-left signal is received at the first shift register when none of the first delay units are activated.

Claim 56

Dependent Claim 25 words

The delay locked loop as recited in claim 45 , wherein a first shift-right signal results in a delay increase of the first delay amount.

Claim 57

Dependent Claim 25 words

The delay locked loop as recited in claim 53 , wherein a first shift-left signal results in a delay decrease of the first delay amount.

Claim 58

Dependent Claim 31 words

The delay locked loop as recited in claim 37 , wherein a second delay unit is activated if all of the first delay units are activated and more delay is desired.

Claim 59

Dependent Claim 74 words

For use in a semiconductor memory, a delay locked loop comprising: a first delay line for selectively delaying a received signal to develop a delayed signal, the first delay line having a capacitance and a plurality of first delay units, the first delay units being adapted to selectively adjust the capacitance of the first delay line; and a second delay line in communication with the first delay line for selectively delaying the delayed signal.

Claim 60

Dependent Claim 74 words

For use in a semiconductor memory, a delay locked loop comprising: a first delay line for selectively delaying a received signal to develop a delayed signal, the first delay line having a capacitance and a plurality of first delay units, the first delay units being adapted to selectively adjust the capacitance of the first delay line; and a second delay line in communication with the first delay line for selectively delaying the delayed signal.

Claim 61

Dependent Claim 22 words

The delay locked loop as recited in claim 56 , wherein the delayed signal is not delayed relative to the received signal.

Claim 62

Dependent Claim 30 words

The delay locked loop as recited in claim 56 , wherein each of the first delay units comprises: a controlled switch; and a capacitor in communication with the controlled switch.

Claim 63

Dependent Claim 17 words

The delay locked loop as recited in claim 58 , wherein the controlled switch comprises a transistor.

Claim 64

Dependent Claim 25 words

The delay locked loop as recited in claim 56 , wherein the second delay line comprises a plurality of second delay units connected in series.

Claim 65

Dependent Claim 41 words

The delay locked loop as recited in claim 60 , wherein each of the second delay units comprises: a first logic element for delaying a received signal; and a second logic element for delaying an output of the first logic element.

Claim 66

Dependent Claim 84 words

The delay locked loop as recited in claim 56 further comprising: a first shift register in communication with the first delay line; and a second shift register in communication with the second delay line, wherein the first shift register triggers a first shift-right signal in response to a first predetermined condition and triggers a first shift-left signal in response to a second predetermined condition, and wherein the second shift register is responsive to at least one of the shift-right signal and the shift-left signal.

Claim 67

Dependent Claim 29 words

The delay locked loop as recited in claim 62 further comprising: a phase comparator coupled to the first shift register; and a delay monitor coupled to the phase comparator.

Claim 68

Dependent Claim 59 words

The delay locked loop as recited in claim 60 , wherein each of the first delay units is adapted to delay the received signal by a first delay amount, each of the second delay units is adapted to delay the delayed signal by a second delay amount, and the second delay amount is greater than the first delay amount.

Claim 69

Dependent Claim 24 words

The delay locked loop as recited in claim 64 , wherein the second delay amount is an integer multiple of the first delay amount.

Claim 70

Dependent Claim 30 words

The delay locked loop as recited in claim 65 , wherein a total delay produced by activating all of the first delay units is less than the second delay amount.

Claim 71

Dependent Claim 70 words

The delay locked loop as recited in claim 62 , wherein the second delay line comprises a plurality of second delay units, each of the first delay units is adapted to delay the received signal by a first delay amount, each of the second delay units is adapted to delay the delayed signal by a second delay amount, and the second delay amount is greater than the first delay amount.

Claim 72

Dependent Claim 38 words

The delay locked loop as recited in claim 67 , wherein the first shift-right signal is produced when all of the first delay units are activated and a second shift-right signal is received at the first shift register.

Claim 73

Dependent Claim 39 words

The delay locked loop as recited in claim 68 , wherein the first delay units are all deactivated when the second shift-right signal is received at the first shift register when all of the first delay units are activated.

Claim 74

Dependent Claim 38 words

The delay locked loop as recited in claim 68 , wherein the first shift-left signal is produced when none of the first delay units are activated and a second shift-left signal is received at the first shift register.

Claim 75

Dependent Claim 39 words

The delay locked loop as recited in claim 70 , wherein the first delay units are all activated when the second shift-left signal is received at the first shift register when none of the first delay units are activated.

Claim 76

Dependent Claim 25 words

The delay locked loop as recited in claim 67 , wherein a first shift-right signal results in a delay increase of the first delay amount.

Claim 77

Dependent Claim 25 words

The delay locked loop as recited in claim 72 , wherein a first shift-left signal results in a delay decrease of the first delay amount.

Claim 78

Dependent Claim 43 words

The delay locked loop as recited in claim 56 , wherein the second delay line includes a plurality of second delay units, and a second delay unit is activated if all of the first delay units are activated and more delay is required.

Claim 79

Dependent Claim 60 words

For use in a semiconductor memory, a method for synchronizing an internal clock signal with an external clock signal comprising the steps of: selectively adjusting a capacitance of a first delay line to delay the external clock signal to develop a delayed signal; and selectively delaying the delayed signal via a second delay line to develop the internal clock signal.

Claim 80

Dependent Claim 60 words

For use in a semiconductor memory, a method for synchronizing an internal clock signal with an external clock signal comprising the steps of: selectively adjusting a capacitance of a first delay line to delay the external clock signal to develop a delayed signal; and selectively delaying the delayed signal via a second delay line to develop the internal clock signal.

Claim 81

Dependent Claim 20 words

The method as recited in claim 75 , wherein the delayed signal is not delayed relative to the received signal.

Claim 82

Dependent Claim 37 words

The method as recited in claim 75 , wherein the step of selectively adjusting the capacitance of the first delay line is performed in first increments, each of the first increments corresponding to a first delay amount.

Claim 83

Dependent Claim 33 words

The method as recited in claim 77 , wherein the step of selectively delaying the delayed signal is performed in second increments, each of the second increments corresponding to a second delay amount.

Claim 84

Dependent Claim 20 words

The method as recited in claim 77 , wherein the second delay amount is greater than the first delay amount.

Claim 85

Dependent Claim 22 words

The method as recited in claim 77 , wherein the second delay amount is an integer multiple of the first delay amount.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2005-11-18	2006-05-20	2006-11-19	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2009-11-18	2010-05-20	2010-11-19	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2013-11-18	2014-05-20	2014-11-19	$7700.00	Window Closed / Lapsed

Delay locked loop for use in semiconductor memory device

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag