Synchronous semiconductor device for adjusting phase offset in a delay locked loop

Claim 2

A synchronous semiconductor device having a delay locked loop, comprising: a replica delay for replicating a delay time of an internal circuit; and a delay controller comprising an anti-fuse circuit for controlling the replicated delay time, the anti-fuse circuit comprising a first control signal generating unit for outputting a first control signal to the replica delay to increase the replicated delay time; and a second control signal generating unit for outputting a second control signal to the replica delay to decrease the replicated delay time.

Claim 3

The synchronous semiconductor device as recited in claim 1 , further comprising a voltage generator for applying voltage to the delay controller.

Claim 4

The synchronous semiconductor device as recited in claim 1 , wherein the first control signal generating unit comprises: an anti-fuse selection unit for outputting a signal determining whether the anti-fuse is shorted by combining an offset adjustment signal inputted through an address pin, an enable signal for an offset mode and a selection signal determining whether the replicated delay time is increased or decreased; an anti-fuse unit for insulating or shorting the anti-fuse according to an output signal of the anti-fuse selection unit; and a first latch for outputting a first control signal by latching the output signal of the anti-fuse unit.

Claim 5

The synchronous semiconductor device as recited in claim 3 , wherein the anti fuse-selection unit comprises: a first NAND gate receiving the offset adjustment signal, the enable signal and the selection signal; a second NAND gate receiving an inversed offset adjustment signal, the enable signal and the selection signal; a first switch for outputting power supply voltage in response to an output signal of the first NAND gate; and a second switch for outputting ground voltage in response to an output signal of the second NAND gate.

Claim 6

The synchronous semiconductor device as recited in claim 4 , wherein the anti-fuse unit comprises: a third switch for applying power supply voltage in repose to a reset signal; and an anti-fuse, which is connected to an output terminal of the anti-fuse selection unit and voltage is applied from the voltage generator, to be shorted when a predetermined voltage difference is generated.

Claim 7

The synchronous semiconductor device as recited in claim 5 , wherein the first latch comprises fourth and fifth inverters for latching voltage of the output terminal of the anti-fuse selection unit.

Claim 8

The synchronous semiconductor device as recited in claim 1 , wherein the replica delay comprises: a clock buffer replica unit for replicating a clock buffer by receiving an external clock signal; a data output buffer replica unit for receiving an output of the clock buffer replica unit and replicating a data output buffer; a plurality of buffers, which are connected in series, for buffering an output of the data output buffer replica unit; a plurality of first unit delay units, which are connected to each output terminal of the plurality of buffers, for delaying the output of the replica delay as much as a first unit delay time in response to the first control signal; and a plurality of second unit delay units, which are connected to each output terminal of the plurality of buffers, for forwarding the output of the replica delay as much as a second unit delay time in response to the second control signal.

Claim 9

The synchronous semiconductor device as recited in claim 7 , wherein each of the first unit delay units comprises: a first capacitor capable of delaying delay time as much as the first unit delay time; and a first transfer gate for connecting the first capacitor with the output terminal of the buffers.

Claim 10

The synchronous semiconductor device as recited in claim 8 , wherein each of the second unit delay units comprises: a second capacitor capable of delaying delay time as much as the second unit delay time; and a second transfer gate for connecting the second capacitor with the output terminal of the buffers.

Claim 11

A synchronous semiconductor device comprising: a clock buffer for receiving an external clock signal and generating an internal clock signal; a delay line for delaying the internal clock signal for synchronization with the external clock signal; a data output buffer for receiving an output of the delay line and outputting the internal clock signal received from the delay line; a replica delay for receiving the output of the delay line, replicating delay time until the external clock signal is outputted as the internal clock signal and adjusting the replicated delay time; a phase detector for comparing the output phase of the replica delay with the output phase of the clock buffer; a phase control unit for controlling delay time of the delay line in response to an output signal of the phase detector, a delay controller comprising an anti-fuse circuit for outputting a control signal to adjust the replicated delay time; the anti-fuse circuit comprising a first control signal generator for outputting a first control signal to the replica delay to increase the replicated delay time; a second control signal generator for outputting a second control signal to the replica delay to decrease the replicated delay time; and a voltage generator for applying voltage to the anti-fuse circuit.

Claim 12

A synchronous semiconductor device comprising: a clock buffer for receiving an external clock signal and generating an internal clock signal; a delay line for delaying the internal clock signal for synchronization with the external clock signal; a data output buffer for receiving an output of the delay line and outputting the internal clock signal received from the delay line; a replica delay for receiving the output of the delay line, replicating delay time until the external clock signal is outputted as the internal clock signal and adjusting the replicated delay time; a phase detector for comparing the output phase of the replica delay with the output phase of the clock buffer; a phase control unit for controlling delay time of the delay line in response to an output signal of the phase detector, a delay controller comprising an anti-fuse circuit for outputting a control signal to adjust the replicated delay time; the anti-fuse circuit comprising a first control signal generator for outputting a first control signal to the replica delay to increase the replicated delay time; a second control signal generator for outputting a second control signal to the replica delay to decrease the replicated delay time; and a voltage generator for applying voltage to the anti-fuse circuit.

Claim 13

The synchronous semiconductor device as recited in claim 10 , wherein the phase control unit comprises: a charge pump for receiving the output of the phase detector and providing charge; and a loop filter for adjusting delay time of the delay line according to the charge inputted from the charge pump.

Claim 14

The synchronous semiconductor device as recited in claim 10 , wherein the first control signal generator comprises: an anti-fuse selection unit for outputting a signal determining whether an anti-fuse is shorted by combining an offset adjustment signal inputted through an address pin, an enable signal for an offset mode and a selection signal determining whether the replicated delay time is increased or decreased; an anti-fuse unit for insulating or shorting the anti-fuse according to an output signal of the anti-fuse selection unit; and a latch for outputting a first control signal by latching the output signal of the anti-fuse unit.

Claim 15

The synchronous semiconductor device as recited in claim 12 , wherein the anti-fuse selection unit comprises: a first NAND gate receiving the offset adjustment signal, the enable signal and the selection signal; a second NAND gate receiving an inversed offset adjustment signal, the enable signal and the selection signal; a first switch for outputting power supply voltage in response to an output signal of the first NAND gate; and a second switch for outputting ground voltage in response to an output signal of the second NAND gate.

Claim 16

The synchronous semiconductor device as recited in claim 13 , wherein the anti-fuse unit comprises: a third switch for applying power supply voltage in response to a reset signal; and an anti-fuse, which is connected to an output terminal of the anti-fuse selection unit and voltage is applied from the voltage generator, to be shorted when a predetermined voltage difference is generated.

Claim 17

The synchronous semiconductor device as recited in claim 14 , wherein the latch comprises fourth and fifth inverters for latching voltage of the output terminal of the anti-fuse selection unit.

Claim 18

The synchronous semiconductor device as recited in claim 10 , wherein the replica delay comprises: a clock buffer replica unit for replicating a clock buffer by receiving an external clock signal; a data output buffer replica unit for receiving an output of the clock buffer replica unit and replicating a data output buffer; a plurality of buffers, which are connected in series, for buffering an output of the data output buffer replica unit; a plurality of first unit delay units, which are connected to each output terminal of the plurality of buffers, for delaying the output of the replica delay as much as a first unit delay time in response to the first control signal; and a plurality of second unit delay units, which are connected to each output terminal of the plurality of buffers, for forwarding the output of the replica delay as much as a second unit delay time in response to the second control signal.

Claim 19

The synchronous semiconductor device as recited in claim 16 , wherein each of the first unit delay units comprises: a first capacitor capable of delaying delay time as much as the first unit delay time; and a first transfer gate for connecting the first capacitor with the output terminal of the buffers.

Claim 20

The synchronous semiconductor device as recited in claim 17 , wherein each of the second unit delay units comprises: a second capacitor capable of delaying delay time as much as the second unit delay time; and a second transfer gate for connecting the second capacitor with the output terminal of the buffers.