Abstract An integrated digital circuit includes an oscillation circuit comprising basic gate circuits having the number of stages proportional to the number of gates existing in the critical path of a synchronized circuit network and capable of controlling an oscillating frequency by at least one control signal line. A synchronized circuit network constructed with basic gate circuits capable of controlling the delay time by at least one control signal line operates synchronously by an oscillation signal transfer line. A control circuit controls the oscillation circuit and the synchronized circuit network using the control signal line so that the frequency of signal input from an externally input signal line is equalized with the frequency of signal from the oscillation circuit. Thus, the synchronized circuit network can be always operated at the frequency obtained from the oscillation signal transfer line even though the delay time of the basic gate circuit varied by variations of the device characteristics and the like.
An integrated digital circuit comprising: at least two registers for constructing a synchronized circuit, and for respectively receiving a first synchronized signal and a second synchronized signal; a circuit network for constructing a logic circuit or a memory circuit and connected between at least two of said registers, the circuit network having a gate circuit, connected between said at least two of said registers, for receiving a first control signal. a control signal generating circuit for generating second and third control signals from said first and second synchronized signals respectively supplied to said registers; a replica delay circuit, coupled to said circuit network, having a plurality of gate circuits connected in a line, a number of said plurality of gate circuits being proportional to a number of gates of a critical path in said circuit network, said replica delay circuit for inputting said second control signal; and a control circuit, coupled to said replica delay circuit and to said circuit network, for outputting said first control signal for controlling said delay times of said circuit network and said replica delay circuit so as to equalize a phase of a signal output from said replica delay circuit with a phase of signal externally input to said integrated digital circuit, determined based on a phase of said third control signal.
Claim 2
Dependent Claim
218 words
An integrated digital circuit comprising: at least two registers for constructing a synchronized circuit, and for respectively receiving a first synchronized signal and a second synchronized signal; a circuit network for constructing a logic circuit or a memory circuit and connected between at least two of said registers, the circuit network having a gate circuit, connected between said at least two of said registers, for receiving a first control signal. a control signal generating circuit for generating second and third control signals from said first and second synchronized signals respectively supplied to said registers; a replica delay circuit, coupled to said circuit network, having a plurality of gate circuits connected in a line, a number of said plurality of gate circuits being proportional to a number of gates of a critical path in said circuit network, said replica delay circuit for inputting said second control signal; and a control circuit, coupled to said replica delay circuit and to said circuit network, for outputting said first control signal for controlling said delay times of said circuit network and said replica delay circuit so as to equalize a phase of a signal output from said replica delay circuit with a phase of signal externally input to said integrated digital circuit, determined based on a phase of said third control signal.