Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
110 words
A signal generator having a selectable frequency which is locked to a reference signal using a phase or frequency locked loop having a controllable oscillator, a detector, a loop filter and a first frequency divider means, wherein the improvement comprises: a second frequency divider means for dividing the output of the oscillator; and a third frequency divider means for changing the frequency of the reference signal to a different value depending upon which value has been used to divide the output signal of the oscillator; wherein the output signal of the oscillator is divided into two or more phase positions with constant phase difference by the second frequency divider means.
Claim 2
Dependent Claim
110 words
A signal generator having a selectable frequency which is locked to a reference signal using a phase or frequency locked loop having a controllable oscillator, a detector, a loop filter and a first frequency divider means, wherein the improvement comprises: a second frequency divider means for dividing the output of the oscillator; and a third frequency divider means for changing the frequency of the reference signal to a different value depending upon which value has been used to divide the output signal of the oscillator; wherein the output signal of the oscillator is divided into two or more phase positions with constant phase difference by the second frequency divider means.
Claim 3
Dependent Claim
146 words
A signal generator having a selectable frequency which is locked to a reference signal using a phase or frequency locked loop having a controllable oscillator, a detector, a loop filter and a first frequency divider means, wherein the improvement comprises: a second frequency divider means for dividing the output of the oscillator; and a third frequency dividing means for changing the frequency of the reference signal to a different value depending upon which value has been used to divide the output signal of the oscillator; wherein the phase of the reference signal is maintained in relation to the phase of the output signal of the oscillator in order to avoid phase jumps when changing the ratios of said frequency dividing means, and the output signal of the oscillator is divided into two or more phase positions with constant phase difference by the second frequency divider means.
Claim 4
Dependent Claim
146 words
A signal generator having a selectable frequency which is locked to a reference signal using a phase or frequency locked loop having a controllable oscillator, a detector, a loop filter and a first frequency divider means, wherein the improvement comprises: a second frequency divider means for dividing the output of the oscillator; and a third frequency dividing means for changing the frequency of the reference signal to a different value depending upon which value has been used to divide the output signal of the oscillator; wherein the phase of the reference signal is maintained in relation to the phase of the output signal of the oscillator in order to avoid phase jumps when changing the ratios of said frequency dividing means, and the output signal of the oscillator is divided into two or more phase positions with constant phase difference by the second frequency divider means.
Claim 5
Dependent Claim
171 words
A signal generator having a selectable frequency which is locked to a reference signal using a phase or frequency locked loop having a controllable oscillator, a detector, a loop filter and a first frequency divider means, wherein the improvement comprises: a second frequency divider means for dividing the output of the oscillator; and a third frequency dividing means for changing the frequency of the reference signal to a different value depending upon which value has been used to divide the output signal to the oscillator; wherein the phase of the reference signal is maintained in relation to the phase of the output signal of the oscillator in order to avoid phase jumps when changing the ratios of said frequency dividing means, the division number of the first frequency divider means within the phase locked loop is determined in accordance with the frequency of the reference signal, and the output signal of the oscillator is divided into two or more phase positions with constant phase difference by the second frequency divider means.
Claim 6
Dependent Claim
171 words
A signal generator having a selectable frequency which is locked to a reference signal using a phase or frequency locked loop having a controllable oscillator, a detector, a loop filter and a first frequency divider means, wherein the improvement comprises: a second frequency divider means for dividing the output of the oscillator; and a third frequency dividing means for changing the frequency of the reference signal to a different value depending upon which value has been used to divide the output signal to the oscillator; wherein the phase of the reference signal is maintained in relation to the phase of the output signal of the oscillator in order to avoid phase jumps when changing the ratios of said frequency dividing means, the division number of the first frequency divider means within the phase locked loop is determined in accordance with the frequency of the reference signal, and the output signal of the oscillator is divided into two or more phase positions with constant phase difference by the second frequency divider means.
Claim 7
Independent Claim
103 words
A method of controlling a frequency synthesizer having a voltage controlled oscillator, a phase detector and a frequency source, which comprises the steps of: dividing the output signal of the voltage controlled oscillator by a first value P; dividing the output signal of the voltage controlled oscillator by a second value N; dividing the input signal from the frequency source by a third value R; and controlling the first, second, and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies; wherein the first value P and the third value R are maintained such that P×R equals a constant value.
Claim 8
Independent Claim
103 words
A method of controlling a frequency synthesizer having a voltage controlled oscillator, a phase detector and a frequency source, which comprises the steps of: dividing the output signal of the voltage controlled oscillator by a first value P; dividing the output signal of the voltage controlled oscillator by a second value N; dividing the input signal from the frequency source by a third value R; and controlling the first, second, and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies; wherein the first value P and the third value R are maintained such that P×R equals a constant value.
Claim 9
Dependent Claim
29 words
A method according to claim 4 further including the step of splitting the output signal into two or more phases by gating out different phase positions from the divider.
Claim 10
Independent Claim
149 words
A method of controlling a frequency synthesizer having a voltage controlled oscillator, a phase detector and a frequency source, which comprises the steps of: dividing the output signal of the voltage controlled oscillator by a first value P; dividing the output signal of the voltage controlled oscillator by a second value N; dividing the input signal from the frequency source by a third value R; controlling the first, second, and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies, wherein the phase of the signal divided by the value R is maintained in relation to the phase of the output signal of the voltage controlled oscillator in order to avoid phase jumps when changing the first, second and third values; and splitting the output signal divided by the first value P into two or more phases by gating out different phase positions from a divider.
Claim 11
Independent Claim
149 words
A method of controlling a frequency synthesizer having a voltage controlled oscillator, a phase detector and a frequency source, which comprises the steps of: dividing the output signal of the voltage controlled oscillator by a first value P; dividing the output signal of the voltage controlled oscillator by a second value N; dividing the input signal from the frequency source by a third value R; controlling the first, second, and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies, wherein the phase of the signal divided by the value R is maintained in relation to the phase of the output signal of the voltage controlled oscillator in order to avoid phase jumps when changing the first, second and third values; and splitting the output signal divided by the first value P into two or more phases by gating out different phase positions from a divider.
Claim 12
Dependent Claim
111 words
An improved frequency synthesizer of the type having a voltage controlled oscillator, a phase detector and a frequency source which further comprises: means for dividing the output signal of the voltage controlled oscillator by a first value P; means for dividing the output signal of the voltage controlled oscillator by a second value N; means for dividing the input signal from the frequency source by a third value R; and means for controlling the first, second and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies; wherein said means for controlling includes means for maintaining the values P and R such that P×R equals a constant value.
Claim 13
Dependent Claim
111 words
An improved frequency synthesizer of the type having a voltage controlled oscillator, a phase detector and a frequency source which further comprises: means for dividing the output signal of the voltage controlled oscillator by a first value P; means for dividing the output signal of the voltage controlled oscillator by a second value N; means for dividing the input signal from the frequency source by a third value R; and means for controlling the first, second and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies; wherein said means for controlling includes means for maintaining the values P and R such that P×R equals a constant value.
Claim 14
Dependent Claim
26 words
A frequency synthesizer according to claim 7 wherein output signals from the means for dividing by a value P are phase-shifted with respect to each other.
Claim 15
Dependent Claim
151 words
A frequency synthesizer of the type having a voltage controlled oscillator, a phase detector and a frequency source which further comprises: means for dividing the output signal of the voltage controlled oscillator by a first value P; means for dividing the output signal of the voltage controlled oscillator by a second value N; means for dividing the input signal from the frequency source by a third value R; and means for controlling the first, second and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies, wherein the phase of the signal divided by the value R is maintained in relation to the phase of the output signal of the voltage controlled oscillator in order to avoid phase jumps when changing the first, second and third values and the output signals from the means for dividing by the first value P are phase-shifted with respect to each other.
Claim 16
Dependent Claim
151 words
A frequency synthesizer of the type having a voltage controlled oscillator, a phase detector and a frequency source which further comprises: means for dividing the output signal of the voltage controlled oscillator by a first value P; means for dividing the output signal of the voltage controlled oscillator by a second value N; means for dividing the input signal from the frequency source by a third value R; and means for controlling the first, second and third values such that the frequency synthesizer synthesizes a range of predetermined frequencies, wherein the phase of the signal divided by the value R is maintained in relation to the phase of the output signal of the voltage controlled oscillator in order to avoid phase jumps when changing the first, second and third values and the output signals from the means for dividing by the first value P are phase-shifted with respect to each other.