US4835491A
Expired / Lapsed
US
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Clock signal generation
Assignee: HP Inc
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Filing: 1988-01-25
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Granted: 1989-05-30
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Expires: 2008-01-25
Abstract
Abstract A clock signal generator is based on a phase locked loop arrangement. The loop includes an adjustable divider. The reference signal for the loop is applied to another adjustable divider. This allows the generation of a wide range of frequencies by appropriate selection of the division ratios.
Inventors
- 👤 John H. Coster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:37
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/22; H03L7/23
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
140 words
A clock signal generator comprising: phase locked loop means for generating a set of clock signals which further comprises a first adjustable dividing means for adjusting the clock signal rate at the output of the loop; means for generating a reference signal for the loop wherein the reference signal generating means comprises a voltage controlled crystal oscillator; second adjustable dividing means coupling the reference signal generating means to the loop for further adjusting the clock signal rate; feedback means for sensing the output frequency of said oscillator and providing correction signals for application to said oscillator to adjust the output frequency of the oscillator to a selected value; and wherein said feedback means comprises a counter, a first microprocessor connected to receive counter output, and a digital to analog converter for applying signals from the first microprocessor to the oscillator.
Claim 2
Dependent Claim
140 words
A clock signal generator comprising: phase locked loop means for generating a set of clock signals which further comprises a first adjustable dividing means for adjusting the clock signal rate at the output of the loop; means for generating a reference signal for the loop wherein the reference signal generating means comprises a voltage controlled crystal oscillator; second adjustable dividing means coupling the reference signal generating means to the loop for further adjusting the clock signal rate; feedback means for sensing the output frequency of said oscillator and providing correction signals for application to said oscillator to adjust the output frequency of the oscillator to a selected value; and wherein said feedback means comprises a counter, a first microprocessor connected to receive counter output, and a digital to analog converter for applying signals from the first microprocessor to the oscillator.
Claim 3
Dependent Claim
32 words
A clock signal generator according to claim 1 wherein the crystal circuit of the oscillator comprises a variable capacitance device, variation of said capacitance device varying the output frequency of said oscillator.
Claim 4
Dependent Claim
20 words
A clock signal generator according to claim 3 wherein the first adjustable dividing means further comprises a dual modulus prescaler.
Claim 5
Dependent Claim
28 words
A clock signal generator according to claim 2 further comprising a third adjustable dividing means for dividing the loop output by 2 n where n is an integer.
Claim 6
Dependent Claim
34 words
A clock signal generator according to claim 4 wherein the first adjustable dividing means, the second adjustable dividing means, and the third adjustable dividing means are adjustable under the control of a second microprocessor.
Claim 7
Dependent Claim
34 words
A clock signal generator according to claim 4 wherein the first adjustable dividing means, the second adjustable dividing means, and the third adjustable dividing means are adjustable under the control of the first microprocessor.
Claim 8
Dependent Claim
37 words
A clock signal generator according to claim 6 wherein the first microprocessor has associated memory means for storing a look-up table containing values of the division ratios of said dividing means for each selectable clock signal frequency.
Claim 9
Dependent Claim
23 words
A clock signal generator according to claim 6 wherein the first microprocessor is also used to adjust the frequency of the crystal oscillator.
Claim 10
Dependent Claim
20 words
A clock signal generator according to claim 1 wherein the first adjustable dividing means further comprises a dual modulus prescaler.
Claim 11
Dependent Claim
28 words
A clock signal generator according to claim 9 further comprising a third adjustable dividing means for dividing the loop output by 2 n where n is an integer.
Claim 12
Dependent Claim
33 words
A clock signal generator according to claim 10 wherein the first adjustable dividing means, the second adjustable dividing means, and the third adjustable dividing means are adjustable under the control of a microprocessor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-29 | 1992-11-28 | 1993-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-29 | 1996-11-28 | 1997-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-29 | 2000-11-28 | 2001-05-30 | $7700.00 | Window Closed / Lapsed |