US4191930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digitally settable frequency generator
Assignee: Wandel and Golterman GmbH and Co
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Filing: 1978-09-13
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Granted: 1980-03-04
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Expires: 1998-09-13
Abstract
Abstract A frequency generator of the digitally settable type comprises several voltage-controlled oscillators, specifically a pair of pilot oscillators and a final oscillator, provided with respective phase-locking loops each including a phase discriminator. The loops of the pilot oscillators further include respective frequency dividers whose step-down ratios are controlled by setting commands stored in associated memories which can be reloaded, under the control of manually or automatically adjustable selectors, only in the presence of an enabling pulse generated by a coincidence circuit with inputs connected to the outputs of a source of reference frequency and of the several stages of a chain of binary dividers connected to that source, certain of these stage outputs delivering comparison frequencies to the phase discriminators fed by the frequency dividers of the pilot oscillators. The phase discriminator associated with the final oscillator has one input connected to a mixer and another input connected to one of the pilot oscillators, the mixer receiving operating frequencies of the other pilot oscillator and of the final oscillator. A timing device such as a monoflop may be triggered by the enabling pulses for temporarily disabling the final phase discriminator, or restricting its dynamic range, to suppress fluctuations in the output frequency due to transient oscillator instability. The emission of such inhibiting pulses may be limited to switching operations involving both pilot oscillators, as upon the occurrence of a denominational carry.
Inventors
- 👤 Peter Harzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:18
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/22; H03L7/23; H03B; H03B23/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
239 words
In a digitally settable frequency generator comprising selector means and a group of electronically adjustable oscillators including a final oscillator producing an output frequency and a plurality of pilot oscillators producing denominational frequencies jointly determining the magnitude of said output frequency, each of said pilot oscillators being provided with a phase-locking loop including a frequency divider with a step-down ratio digitally variable by said selector means and an associated phase discriminator with a first input connected to receive a variable frequency from said frequency divider and with a second input connected to receive one of a plurality of fixed comparison frequencies, said final oscillator being provided with control means connected between a frequency-adjusting input thereof and said pilot oscillators, the combination therewith of a reference-frequency source with output connection to the second inputs of the phase discriminators associated with said pilot oscillators for supplying same with coherent frequencies of different magnitudes constituting said comparison frequencies, pulse-generating means connected to said source for producing a train of unblocking pulses shorter than a cycle of the highest comparison frequency and separated by intervals longer than a half-cycle of the lowest comparison frequency, and memory means inserted between said selector means and said frequency dividers for storing setting commands determining the step-down ratios thereof, said memory means having enabling inputs connected to said pulse-generating means for preventing a change in the stored setting commands except in the presence of an unblocking pulse.
Claim 2
Dependent Claim
239 words
In a digitally settable frequency generator comprising selector means and a group of electronically adjustable oscillators including a final oscillator producing an output frequency and a plurality of pilot oscillators producing denominational frequencies jointly determining the magnitude of said output frequency, each of said pilot oscillators being provided with a phase-locking loop including a frequency divider with a step-down ratio digitally variable by said selector means and an associated phase discriminator with a first input connected to receive a variable frequency from said frequency divider and with a second input connected to receive one of a plurality of fixed comparison frequencies, said final oscillator being provided with control means connected between a frequency-adjusting input thereof and said pilot oscillators, the combination therewith of a reference-frequency source with output connection to the second inputs of the phase discriminators associated with said pilot oscillators for supplying same with coherent frequencies of different magnitudes constituting said comparison frequencies, pulse-generating means connected to said source for producing a train of unblocking pulses shorter than a cycle of the highest comparison frequency and separated by intervals longer than a half-cycle of the lowest comparison frequency, and memory means inserted between said selector means and said frequency dividers for storing setting commands determining the step-down ratios thereof, said memory means having enabling inputs connected to said pulse-generating means for preventing a change in the stored setting commands except in the presence of an unblocking pulse.
Claim 3
Dependent Claim
76 words
The combination defined in claim 1 wherein said output connections extend from stages of a multistage divider chain connected to said source, said divider chain having an entrance stage upstream of a stage output carrying the highest comparison frequency and an exit stage downstream of a stage output carrying the lowest comparison frequency, said pulse-generating means comprising a coincidence circuit with inputs connected to said source and to all the stage outputs of said divider chain.
Claim 4
Dependent Claim
94 words
The combination defined in claim 1 or 2 wherein said pilot oscillators include a first oscillator and a second oscillator, said control means comprising a mixer with inputs connected to said final oscillator and to said first oscillator, said mixer having an output circuit including filter means for passing only a frequency synthesized from said output frequency and from the denominational frequency generated by said first oscillator, and a further phase discriminator with input connections extending to said filter means and to said second oscillator and with an output connection to said frequency-adjusting input.
Claim 5
Dependent Claim
58 words
The combination defined in claim 3, further comprising timing means connected to said pulse-generating means and triggerable by said unblocking pulse to emit inhibiting pulses fed to said further phase discriminator for at least reducing the ability of the latter, over an off-normal period substantially shorter than said intervals, to alter the operating frequency of said final oscillator.
Claim 6
Dependent Claim
37 words
The combination defined in claim 4 wherein said further phase discriminator is deactivable by said inhibiting pulses and is provided with integrating circuitry for preserving, during said off-normal period, a control variable fed to said frequency-adjusting input.
Claim 7
Dependent Claim
48 words
The combination defined in claim 4, further comprising gating means in series with said timing means and selection-responsive means connected to said gating means for permitting the emission of an inhibiting pulse only in the presence of a predetermined switching criterion in the variation of said step-down ratio.
Claim 8
Dependent Claim
45 words
The combination defined in claim 6 wherein said selection-responsive means comprises sensing means connected to said memory means for allowing the emission of an inhibiting pulse only upon simultaneous changes in the step-down ratios of the frequency dividers associated with said first and second oscillators.
Claim 9
Dependent Claim
57 words
The combination defined in claim 6 wherein said selection-responsive means comprises respective output leads from the memory means associated with said first and second oscillators for allowing the emission of an inhibiting pulse only upon energization of at least one of said output leads in response to a setting command involving the generation of a denominational carry.
Claim 10
Dependent Claim
46 words
The combination defined in claim 6 wherein said selector means includes a calculator adapted to convert selection signals into said setting commands, said selection-responsive means comprising an output connection from said calculator energizable in response to a setting command involving the generation of a denominational carry.
Claim 11
Dependent Claim
25 words
The combination defined in claim 3 wherein the input connection of said further phase discriminator extending to said second oscillator includes an additional frequency divider.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-03-04 | 1983-09-03 | 1984-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-03-04 | 1987-09-03 | 1988-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-03-04 | 1991-09-03 | 1992-03-04 | $7700.00 | Window Closed / Lapsed |