Signal delay apparatus employing a phase locked loop

Claim 1

A circuit for providing an on-chip substantially constant delay in a signal path, comprising: a delay cell within the signal path requiring a substantially constant delay, the delay cell including a CMOS differential amplifier having pullup and pulldown currents being controlled by first and second control signals, respectively; and a delay lock loop for maintaining the substantially constant delay through the delay cell; the delay lock loop including: a delay line comprising a plurality of serially connected delay cells identical to the delay cell within the signal path, an input for receiving a reference clock signal, and an output for providing a delayed clock signal; a phase detector connected to receive the delayed clock signal and the reference clock signal and having outputs indicative of a phase difference between the delayed clock signal relative to the reference clock signal; a charge pump connected to the outputs of the phase detector and having a capacitor for providing an output signal therefrom; and a bias generator having an input connected to receive the output signal of the charge pump for providing the first and second control signals.