Data delay circuit and clock extraction circuit using the same

Claim 2

A data delay circuit connectable to receive first and second voltages, to receive input data having a first polarity and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and comprising: a first transistor having a base connectable to receive the input data, an emitter and a collector; a second transistor having a base connectable to receive the input data, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistors and to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor,; and first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage, delayed input data being drawn from the collectors of said third and fourth transistors.

Claim 3

A data delay circuit as claimed in claim 1, further comprising: first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of the inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.

Claim 4

A data delay circuit as claimed in claim 1, further comprising: a second constant-current source coupled to the collector of said first transistor and to receive the first voltage, and a third constant-current source coupled to the collector of said second transistor and to receive the first voltage.

Claim 5

A data delay circuit as claimed in claim 1, wherein said capacitor comprises a plurality of capacitors connected in series.

Claim 6

A data delay circuit as claimed in claim 1, wherein said capacitor comprises a plurality of capacitors connected in parallel.

Claim 7

A data delay circuit as claimed in claim 1, wherein said capacitor comprises a variable-capacitance diode having a variable capacitance dependent on the desired delay time.

Claim 8

A data delay circuit as claimed in claim 1, wherein said constant-current source includes means for providing a variable constant current to vary the amplitude said delayed input data.

Claim 9

A data delay circuit as claimed in claim 1, further comprising: fifth and sixth transistors coupled to the collectors of said third and fourth transistors.

Claim 10

A data delay circuit as claimed in claim 2, wherein said first means comprises: differential pair means for amplifying the input data to generate a current signal and an inverted current signal; first transistor pair means for dividing the current signal into a first current signal and a second current signal; and second transistor pair means for dividing the inverted current signal into a third current signal and a fourth current signal.

Claim 11

A data delay circuit as claimed in claim 2, wherein said second mens comprises: differential pair means for amplifying the inverted input data to generated a current signal and an inverted current signal; first transistor pair means for dividing the current signal into a first current signal and a second current signal in proportion to a reference voltage corresponding to the adjusted amplitude level; and second transistor pair means for dividing the inverted current signal into a third current signal and a fourth current signal in proportion to the reference voltage corresponding to the adjusted amplitude level.

Claim 12

A data delay circuit connectable to receive first and second voltages, to receive input data having a first plurality and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and comprising: a plurality of delay circuits cascaded, each of said delay circuits including: a first transistor having a base connectable to receive the input data, an emitter and a collector; a second transistor having abase connectable to receive the input data, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistors and to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor; first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage; delayed input data being drawn from the collectors of said third and fourth transistors; first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of the inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.

Claim 13

A data delay circuit connectable to receive first and second voltages, to receive input data having a first plurality and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and comprising: a plurality of delay circuits cascaded, each of said delay circuits including: a first transistor having a base connectable to receive the input data, an emitter and a collector; a second transistor having abase connectable to receive the input data, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistors and to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor; first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage; delayed input data being drawn from the collectors of said third and fourth transistors; first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of the inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.

Claim 14

A data delay circuit as claimed in claim 11, wherein each of said delay circuits comprises; a second constant-current source coupled to the collector of said first transistor and to receive the first voltage, and a third constant-current source coupled to the collector of said second transistor and to receive the first voltage.

Claim 15

A timing extraction circuit comprising: data delay circuit connectable to receive first and second voltages, to receive input data having a first polarity and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and having an input terminal and an output terminal; and an exclusive-OR gate having a first input terminal connectable to receive the input data, a second input terminal coupled to the output terminal of said data delay circuit, and an output terminal which outputs an extracted pulse, said data delay circuit includes: a first transistor having a base connectable to receive the input data, an emitter and a collector; a second transistor having a base connectable to receive the input data from said input terminal of said data delay circuit, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistors and to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor; first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage; delayed input data being drawn from the collectors of said third and fourth transistors through said output terminal of said data delay circuit; first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of then inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.

Claim 16

A timing extraction circuit comprising: data delay circuit connectable to receive first and second voltages, to receive input data having a first polarity and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and having an input terminal and an output terminal; and an exclusive-OR gate having a first input terminal connectable to receive the input data, a second input terminal coupled to the output terminal of said data delay circuit, and an output terminal which outputs an extracted pulse, said data delay circuit includes: a first transistor having a base connectable to receive the input data, an emitter and a collector; a second transistor having a base connectable to receive the input data from said input terminal of said data delay circuit, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistors and to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor; first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage; delayed input data being drawn from the collectors of said third and fourth transistors through said output terminal of said data delay circuit; first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of then inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.

Claim 17

A timing extraction circuit as claimed in claim 13, wherein each of said delay circuits comprises: a second constant-current source coupled to the collector of said first transistor and to receive the first voltage, and a third constant-current source coupled to the collector of said second transistor and to receive the first voltage.

Claim 18

A timing circuit comprising: a timing extraction circuit receiving input data and outputting an extracted pulse; narrow-bandpass filter means for filtering said extracted pulse to generate a filtered extracted pulse; and limiter amplifying means for amplifying and limiting an amplitude level of said filtered extracted pulse, said timing extraction circuit including: data delay circuit connectable to receive first and second voltages, to receive input data having a first polarity and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and having an input terminal and an output terminal; and an exclusive-OR gate having a first input terminal connectable to receive the input data, a second input terminal coupled to the output terminal of said data delay circuit, and an output terminal which outputs an extracted pulse, said data delay circuit including: a first transistor having a base connectable to receive input data, an emitter and a collector; a second transistor having a base connectable to receive the input data from said input terminal of said data delay circuit, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistor sand to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor; first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage; delayed input data being drawn from the collectors of said third and fourth transistors through said output terminal of said data delay circuit; first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of the inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.

Claim 19

A timing circuit comprising: a timing extraction circuit receiving input data and outputting an extracted pulse; narrow-bandpass filter means for filtering said extracted pulse to generate a filtered extracted pulse; and limiter amplifying means for amplifying and limiting an amplitude level of said filtered extracted pulse, said timing extraction circuit including: data delay circuit connectable to receive first and second voltages, to receive input data having a first polarity and to receive control data having a second polarity opposite the first polarity and having an amplitude level corresponding to a desired delay time of the input data, and having an input terminal and an output terminal; and an exclusive-OR gate having a first input terminal connectable to receive the input data, a second input terminal coupled to the output terminal of said data delay circuit, and an output terminal which outputs an extracted pulse, said data delay circuit including: a first transistor having a base connectable to receive input data, an emitter and a collector; a second transistor having a base connectable to receive the input data from said input terminal of said data delay circuit, an emitter and a collector; a constant-current source coupled to the emitters of said first and second transistor sand to receive the first voltage; a capacitor coupled between the collector of said first transistor and the collector of said second transistor; a third transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said first transistor; a fourth transistor having a base connectable to receive the control data, a collector, and an emitter coupled to the collector of said second transistor; first and second load resistors respectively coupled to the collectors of said third and fourth transistor and to receive the second voltage; delayed input data being drawn from the collectors of said third and fourth transistors through said output terminal of said data delay circuit; first means for generating inverted input data based on the input data; and second means for adjusting an amplitude level of the inverted input data in accordance with the desired delay time and for providing the delayed inverted input data as the control data.