Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure

Claim 2

A clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal, the clock generating circuit comprising: a mirror delay circuit for receiving the reference clock signal and delaying the reference clock signal by a predetermined mirror delay time to generate a delay clock signal; a multiplexer for selecting and outputting one of the delay clock signal and the internal clock signal in response to a predetermined toggle control signal; a first divider for dividing the signal transmitted from the multiplexer by 2 to generate a first divided signal; a second divider for dividing the reference clock signal by 2 to generate a second divided signal; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; and a fast comparator for providing a pre-clock signal for generating the internal clock signal, in response to the first and the second pumping signals, wherein the pre-clock signal responds to a voltage level of one of the first and the second pumping signals with respect to a predetermined reference voltage.

Claim 3

The clock generating circuit of claim 1 , wherein N is 1.

Claim 4

The clock generating circuit of claim 1 , wherein the first divided signal is obtained by dividing one of a delay clock signal and the internal clock signal by 2N, the delay clock signal being obtained by delaying the reference clock signal by a predetermined delay time, and the second divided signal is obtained by dividing the reference clock signal by 2N.

Claim 5

The clock generating circuit of claim 1 , wherein the voltage level of the first pumping signal rises at a predetermined first time changing rate in response to the rising edge of the first divided signal and falls at the first time changing rate in response to the falling edge of the second divided signal, and the voltage level of the second pumping signal rises at a predetermined second time changing rate in response to the falling edge of the first divided signal and falls at the second time changing rate in response to the rising edge of the second divided signal.

Claim 6

The clock generating circuit of claim 4 , wherein the first time changing rate is identical to the second time changing rate.

Claim 7

The clock generating circuit of claim 1 , wherein the internal clock signal is activated when the voltage level of at least one of the first and the second pumping signals is lower than the reference voltage level.

Claim 8

The clock generating circuit of claim 1 , wherein the multiplexer outputs the delay clock signal in a first stage of operation and outputs the internal clock signal in a second stage of operation after predetermined clock cycles from the beginning of the first stage of operation.

Claim 9

The clock generating circuit of claim 1 , wherein the first and the second dividers are T flip-flops.

Claim 10

The clock generating circuit of claim 1 , wherein the linear current pump comprises: a first pumping unit for receiving the first and the second divided signals and generating the first pumping signal, wherein the first pumping signal is controlled to be at a reference voltage level when the first divided signal is in a first logic state and the second divided signal is in a second logic state, wherein the voltage level of the first pumping signal rises at a first-time changing rate in response to the transition of the second logic state of the first divided signal and falls at the first-time changing rate in response to the transition of the first logic state of the second divided signal; and a second pumping unit for receiving the first and the second divided signals and generating the second pumping signal, wherein the second pumping signal is controlled to be at a reference voltage level when the first divided signal is in the second logic state and the second divided signal is in the first logic state, wherein the voltage level of the second pumping signal rises at a second-time changing rate in response to the transition of the first logic state of the first divided signal and falls at the second-time changing rate in response to the transition of the second logic state of the second divided signal.

Claim 11

The clock generating circuit of claim 9 , wherein the first-time changing rate is identical to the second-time changing rate.

Claim 12

The clock generating circuit of claim 1 , wherein the fast comparator comprises: a first comparator for comparing a voltage level of the first pumping signal with the reference voltage to generate a first comparison signal; a second comparator for comparing a voltage level of the second pumping signal with the reference voltage to generate a second comparison signal; and a logic operation unit for performing a logic operation on the first and the second comparison signals to provide the pre-clock signal.

Claim 13

The clock generating circuit of claim 1 , further comprising a driver for driving the pre-clock signal to generate the internal clock signal.

Claim 14

A clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal, the clock generating circuit comprising: a controller for receiving the internal clock signal and the reference clock signal and generating first and second divided signals, wherein the first and the second divided signals have different phases and a 1/(2N) (N is a natural number) frequency of the reference clock signal; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; a comparator for providing a pre-clock signal in response to the first and the second pumping signals, wherein the pre-clock signal responds to a voltage level of one of the first and the second pumping signals with respect to a reference voltage; a selection delay unit for delaying the pre-clock signal by a predetermined variable delay time to generate the internal clock signal; and a delay regulator for providing a duty control signal for controlling the duty ratio of the internal clock signal to the selection delay unit.

Claim 15

A clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal, the clock generating circuit comprising: a controller for receiving the internal clock signal and the reference clock signal and generating first and second divided signals, wherein the first and the second divided signals have different phases and a 1/(2N) (N is a natural number) frequency of the reference clock signal; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; a comparator for providing a pre-clock signal in response to the first and the second pumping signals, wherein the pre-clock signal responds to a voltage level of one of the first and the second pumping signals with respect to a reference voltage; a selection delay unit for delaying the pre-clock signal by a predetermined variable delay time to generate the internal clock signal; and a delay regulator for providing a duty control signal for controlling the duty ratio of the internal clock signal to the selection delay unit.

Claim 16

The clock generating circuit of claim 13 , wherein the delay regulator generates the duty control signal in response to the pre-clock signal and a predetermined duty reference signal to control the duty ratio of the internal clock signal to be identical to the duty ratio of the reference clock signal.

Claim 17

The clock generating circuit of claim 14 , further comprising a duty reference signal generator for generating the duty reference signal.

Claim 18

The clock generating circuit of claim 15 , wherein the duty reference signal generator comprises: a duty controller for receiving the reference clock signal and generating first and second duty divided signals, wherein the first and the second duty divided signals have different phases and a 1/(2N) frequency of the reference clock signal; a duty linear current pump for generating first and the second duty pumping signals in response to the first and the second duty divided signals, wherein each of the first and the second duty pumping signals has a level-up time rate and a level-down time rate which are the same; and a duty fast comparator for generating the duty reference signal in response to the first and the second duty pumping signals.

Claim 19

The clock generating circuit of claim 16 , wherein the duty controller comprises: a mirror delay circuit for receiving the reference clock signal and delaying it a predetermined mirror delay time to generate a delay clock signal; a first divider for dividing the delay clock signal by 2; and a second divider for dividing the reference clock signal by 2.

Claim 20

The clock generating circuit of claim 17 , wherein the duty fast comparator comprises: a comparing circuit for comparing the first duty pumping signal with the second duty pumping signal to generate first and second duty comparison signals having opposite logic states; and a logic operation unit which is enabled by the first logic state of the delay clock signal, for performing an OR operation on the first and the second comparison signals to provide the duty reference signal.

Claim 21

A clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal, the clock generating circuit comprising: a controller for receiving the internal clock signal and the reference clock signal and generating first and second divided signals, wherein the controller comprises a multiplexer for selecting one of a delay clock signal and the internal clock signal according to a predetermined toggle control signal, the delay clock signal being obtained by delaying the reference clock signal by a predetermined delay time, wherein the first divided signal is obtained by dividing the selected signal of the delay clock signal and the internal clock signal by 2N, and the second divided signal is obtained by dividing the reference clock signal by 2N; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; and a fast comparator for providing a pre-clock signal for generating the internal clock signal, in response to the first and the second pumping signals, wherein the pre-clock signal is activated when the voltage level of at least one of the first and the second pumping signals is lower than a reference voltage.

Claim 22

A clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal, the clock generating circuit comprising: a controller for receiving the internal clock signal and the reference clock signal and generating first and second divided signals, wherein the controller comprises a multiplexer for selecting one of a delay clock signal and the internal clock signal according to a predetermined toggle control signal, the delay clock signal being obtained by delaying the reference clock signal by a predetermined delay time, wherein the first divided signal is obtained by dividing the selected signal of the delay clock signal and the internal clock signal by 2N, and the second divided signal is obtained by dividing the reference clock signal by 2N; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; and a fast comparator for providing a pre-clock signal for generating the internal clock signal, in response to the first and the second pumping signals, wherein the pre-clock signal is activated when the voltage level of at least one of the first and the second pumping signals is lower than a reference voltage.

Claim 23

The clock generating circuit of claim 17 , wherein, at a first stage of an operation, the multiplexer selects the delay clock signal to generate the first divided signal, wherein, at a second stage of an operation following predetermined clock cycles from the beginning of the first stage of operation, the multiplexer selects the internal clock signal to generate the first divided signal.