US6584021B2
Expired / Lapsed
US
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Semiconductor memory having a delay locked loop
Assignee: Polaris Innovations Ltd
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Filing: 2002-01-15
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Granted: 2003-06-24
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Expires: 2022-01-15
Abstract
Abstract A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output drivers with an externally supplied clock signal. An updating of the delay locked loop is suppressed during a Read state of the semiconductor memory. An appropriate control signal is produced by a state machine and is supplied to the delay locked loop. The synchronization of the data output with the supplied clock signal can be achieved in a precise manner and requires only simple circuitry.
Inventors
- 👤 Patrick Heyne
- 👤 Thomas Hein
- 👤 Torsten Partsch
- 👤 Marx Thilo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:14
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
196 words
A semiconductor memory, comprising: a memory cell array including dynamic memory cells; an output connection operatively connected to said memory cell array for outputting data values stored in said dynamic memory cells; a state machine selectively having an operating state selected from the group consisting of Read, Write and Refresh and having a signal connection providing a control signal for displaying the operating state Read; a delay locked loop operatively connected to said state machine, said delay locked loop receiving an input clock signal and providing a delayed output clock signal, said delay locked loop having a signal connection for receiving the control signal from said state machine, said delay locked loop being configured to be actuated by the control signal in order to suppress a change in a delay time between the input clock signal and the delayed output clock signal during the operating state Read; and an output driver operatively connected to said delay locked loop, said output driver being configured to be actuated by the delayed output clock signal in order to provide, at said output connection, data values read from said dynamic memory cells in sync with the delayed output clock signal.
Claim 2
Dependent Claim
196 words
A semiconductor memory, comprising: a memory cell array including dynamic memory cells; an output connection operatively connected to said memory cell array for outputting data values stored in said dynamic memory cells; a state machine selectively having an operating state selected from the group consisting of Read, Write and Refresh and having a signal connection providing a control signal for displaying the operating state Read; a delay locked loop operatively connected to said state machine, said delay locked loop receiving an input clock signal and providing a delayed output clock signal, said delay locked loop having a signal connection for receiving the control signal from said state machine, said delay locked loop being configured to be actuated by the control signal in order to suppress a change in a delay time between the input clock signal and the delayed output clock signal during the operating state Read; and an output driver operatively connected to said delay locked loop, said output driver being configured to be actuated by the delayed output clock signal in order to provide, at said output connection, data values read from said dynamic memory cells in sync with the delayed output clock signal.
Claim 3
Dependent Claim
42 words
The semiconductor memory according to claim 1 , including a data signal path, said output driver being coupled to said dynamic memory cells via said data signal path for providing the data values read from said memory cells at said output connection.
Claim 4
Dependent Claim
57 words
The semiconductor memory according to claim 2 , wherein the delayed output clock signal has a rising edge and a falling edge, said output driver provides, at said output connection, the data values read from said dynamic memory cells in sync with one of the rising edge and the falling edge of the delayed output clock signal.
Claim 5
Dependent Claim
29 words
The semiconductor memory according to claim 1 , wherein said dynamic memory cells each include a transistor and a capacitor coupled to said data signal path via said transistor.
Claim 6
Dependent Claim
71 words
The semiconductor memory according to claim 1 , wherein: said state machine is configured to receive an address representing one of said dynamic memory cells and an operating command, the address and the operating command are provided as external signals; and said state machine adopts a current operating state based on a preceding operating state, on the address representing said one of said dynamic memory cells, and on the operating command.
Claim 7
Dependent Claim
167 words
The semiconductor memory according to claim 1 , wherein: said delay locked loop has an input connection, an output connection, and a signal section with a controllable delay time, said signal section is connected between said input connection of said delay locked loop and said output connection of said delay locked loop; said delay locked loop has a delay element having an input connected to said output; connection of said delay locked loop, a phase detector connected, on an input side thereof, to said input connection of said delay locked loop and to an output of said delay element, and said delay locked loop has a filter having an input connected to said phase detector and said filter has an output connected to said signal section for controlling a delay time; and said delay locked loop is configured such that a change of the controllable delay time of said signal section is selectively turned on and turned off via said signal connection of said delay locked loop.
Claim 8
Dependent Claim
127 words
The semiconductor memory according to claim 6 , including: first circuit elements connected between a connection for the input clock signal and said input connection of said delay locked loop, said first circuit elements having a delay time; second circuit elements connected between said output connection of said delay locked loop and said output driver, said second circuit elements having a delay time; and said delay element has a delay time corresponding to the delay time of said first circuit elements and to the delay time of said second circuit elements in order to synchronize the input clock signal with the data values read out at said output connection operatively connected to said memory cell array for outputting the data values stored in said dynamic memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-23 | 2006-12-23 | 2007-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-23 | 2010-12-23 | 2011-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-23 | 2014-12-23 | 2015-06-24 | $7700.00 | Window Closed / Lapsed |