US6487648B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
SDRAM controller implemented in a PLD
Assignee: Xilinx Inc
•
Filing: 1999-12-15
•
Granted: 2002-11-26
•
Expires: 2019-12-15
Abstract
Abstract A programmable logic device (PLD) implementing an SDRAM controller is provided. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. The configurable logic of the PLD also forms a state machine to operate the controller and the interface. In accordance with the present invention, dedicated circuits of the PLD optimize performance of the SDRAM controller. These dedicated circuits include two delay locked loops (DLLs) which eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock.
Inventors
- 👤 Joseph H. Hassoun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
164 words
A method of implementing a synchronous dynamic random access memory (SDRAM) controller in a programmable logic device (PLD), the method comprising: using configurable logic of the PLD to form an interface between a system and an SDRAM; using the configurable logic to form a state machine to operate the controller and the interface; and eliminating skew between a system clock, a global clock in the PLD, and an SDRAM clock using dedicated circuits of the PLD, wherein using the configurable logic to form a state machine includes the following steps during a Write operation: if the system issues a WRITE command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Write Wait for Ras-to-Cas Delay state; and if the system issues a WRITE command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Write Command state in which the controller issues data and a WRITE command to the SDRAM.
Claim 2
Independent Claim
164 words
A method of implementing a synchronous dynamic random access memory (SDRAM) controller in a programmable logic device (PLD), the method comprising: using configurable logic of the PLD to form an interface between a system and an SDRAM; using the configurable logic to form a state machine to operate the controller and the interface; and eliminating skew between a system clock, a global clock in the PLD, and an SDRAM clock using dedicated circuits of the PLD, wherein using the configurable logic to form a state machine includes the following steps during a Write operation: if the system issues a WRITE command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Write Wait for Ras-to-Cas Delay state; and if the system issues a WRITE command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Write Command state in which the controller issues data and a WRITE command to the SDRAM.
Claim 3
Dependent Claim
26 words
The method of claim 1 , wherein after the WRITE command is issued, the controller continues to provide data in a Write state until burst end.
Claim 4
Dependent Claim
17 words
The method of claim 2 , wherein after burst end, the controller returns to an Idle state.
Claim 5
Independent Claim
159 words
A method of implementing a synchronous dynamic random access memory (SDRAM) controller in a programmable logic device (PLD), the method comprising: using configurable logic of the PLD to form an interface between a system and an SDRAM; using the configurable logic to form a state machine to operate the controller and the interface; and eliminating skew between a system clock, a global clock in the PLD, and an SDRAM clock using dedicated circuits of the PLD, wherein using the configurable logic to form a state machine includes the following steps during a Read operation: if the system issues a READ command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Read Wait for Ras-to-Cas Delay state; and if the system issues a READ command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Read Command state and issues a READ command to the SDRAM.
Claim 6
Independent Claim
159 words
A method of implementing a synchronous dynamic random access memory (SDRAM) controller in a programmable logic device (PLD), the method comprising: using configurable logic of the PLD to form an interface between a system and an SDRAM; using the configurable logic to form a state machine to operate the controller and the interface; and eliminating skew between a system clock, a global clock in the PLD, and an SDRAM clock using dedicated circuits of the PLD, wherein using the configurable logic to form a state machine includes the following steps during a Read operation: if the system issues a READ command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Read Wait for Ras-to-Cas Delay state; and if the system issues a READ command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Read Command state and issues a READ command to the SDRAM.
Claim 7
Dependent Claim
24 words
The method of claim 4 , wherein after the Read Command state, the controller automatically enters a Read Command, Wait for Cas Latency state.
Claim 8
Dependent Claim
27 words
The method of claim 5 , wherein after the Read Command, Wait for Cas Latency state, the controller reads data in a Read state until burst end.
Claim 9
Dependent Claim
17 words
The method of claim 6 , wherein after burst end, the controller returns to an Idle state.
References Cited (Backward Citations)
US5535342A
Cited
US5319252A
Cited
US5331220A
Cited
US5737612A
Cited
US6130552A
Cited
US5717644A
Cited
US5982697A
Cited
US5926838A
Cited
US5995424A
Cited
US6043677A
Cited
US5917761A
Cited
US6233694B1
Cited
US5959929A
Cited
US6154078A
Cited
US6107826A
Cited
US6219747B1
Cited
US6191613B1
Cited
US6201754B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-25 | 2006-05-27 | 2006-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-25 | 2010-05-27 | 2010-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-25 | 2014-05-27 | 2014-11-26 | $7700.00 | Window Closed / Lapsed |