Power-on reset control circuit

Claim 2

A power-on reset control circuit comprising: a control emulation circuit including a plurality of integrated circuits cascaded together and capable of transmitting a control signal from a last one of the plurality of integrated circuits on a control line to indicate that the plurality of integrated circuits are operating correctly; and a control verification circuit coupled to said control emulation circuit through said control line, wherein said control verification circuit is capable of deactivating a global power-on reset signal upon receiving both an inactive local power-on reset signal indicating that a power source is providing a voltage at an operating threshold level, and said control signal in an inactive state.

Claim 3

A computer system comprising: processor means for processing information within said computer system; memory means for storing data to control the processing performed by said processor means; a first bus means coupled between said memory means and said processing means for transferring information between at least said memory means and said processor means; peripheral means for performing a selected operation, said peripheral means being coupled to a second bus means; a controlling means for enabling information to be transferred between said first and second bus means, said controlling means including a first plurality of integrated circuits reset by an active global power-on reset signal and at least one integrated circuit functioning independently of the power-on reset signal, a power-on reset control circuit coupled to a power source providing a ramping voltage following power up, the power-on reset control circuit comprising: a control emulation circuit including a plurality of integrated circuits cascaded together and capable of transmitting a control signal from a last one of the plurality of integrated circuits through a first control line to indicate that the plurality of integrated circuits are operating correctly; and a control verification circuit coupled to said control emulation circuit through said first control line, wherein said control verification circuit is capable of deactivating the global power-on reset signal upon receiving both an inactive local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level, and said control signal in an inactive state.

Claim 4

A computer system comprising: processor means for processing information within said computer system; memory means for storing data to control the processing performed by said processor means; a first bus means coupled between said memory means and said processing means for transferring information between at least said memory means and said processor means; peripheral means for performing a selected operation, said peripheral means being coupled to a second bus means; a controlling means for enabling information to be transferred between said first and second bus means, said controlling means including a first plurality of integrated circuits reset by an active global power-on reset signal and at least one integrated circuit functioning independently of the power-on reset signal, a power-on reset control circuit coupled to a power source providing a ramping voltage following power up, the power-on reset control circuit comprising: a control emulation circuit including a plurality of integrated circuits cascaded together and capable of transmitting a control signal from a last one of the plurality of integrated circuits through a first control line to indicate that the plurality of integrated circuits are operating correctly; and a control verification circuit coupled to said control emulation circuit through said first control line, wherein said control verification circuit is capable of deactivating the global power-on reset signal upon receiving both an inactive local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level, and said control signal in an inactive state.

Claim 5

The computer system according to claim 2, wherein the emulation circuitry includes a sense amplifier.

Claim 6

The computer system according to claim 2, wherein said control verification circuit includes a power-on reset generation circuit capable of deactivating said local power-on reset signal upon detecting that the power source is providing said operating threshold voltage.

Claim 7

The computer system according to claim 4, wherein said control verification circuit further includes a logic element having first and second input ports, said power-on reset generation circuit being coupled to said first input port through a power-on reset line for enabling transmission of said local power-on reset signal into said first input port and said control emulation circuit being coupled to said second input port through said first control line.

Claim 8

The computer system according to claim 5, wherein said logic element includes a set-reset latch with said first input port setting said set-reset latch and said second input port resetting said set-reset latch.

Claim 9

The power-on reset control circuit of claim 1, wherein the plurality of integrated circuits are cascaded together to limit current of the power supply during activation of the global power-on reset signal.