US6154078A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor buffer circuit with a transition delay circuit
Assignee: Micron Technology Inc
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Filing: 1998-01-07
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Granted: 2000-11-28
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Expires: 2018-01-07
Abstract
Abstract The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.
Inventors
- 👤 Eric J. Stave
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
72 words
A transition delay circuit, comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and a gate terminal connected to said common node.
Claim 2
Dependent Claim
72 words
A transition delay circuit, comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and a gate terminal connected to said common node.
Claim 3
Dependent Claim
18 words
The transition delay circuit of claim 1 wherein said delay circuit comprises a plurality of inverters connected serially.
Claim 4
Dependent Claim
16 words
The transition delay circuit of claim 1 wherein said delay circuit comprises three inverters connected serially.
Claim 5
Dependent Claim
99 words
A transition delay circuit, comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a first capacitor having majority and minority carriers, said first capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and a second capacitor having majority and minority carriers opposite of said majority and minority carriers of said first capacitor, said second capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node.
Claim 6
Dependent Claim
99 words
A transition delay circuit, comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a first capacitor having majority and minority carriers, said first capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and a second capacitor having majority and minority carriers opposite of said majority and minority carriers of said first capacitor, said second capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node.
Claim 7
Dependent Claim
91 words
A buffer circuit, comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit.
Claim 8
Dependent Claim
91 words
A buffer circuit, comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit.
Claim 9
Dependent Claim
59 words
The buffer circuit of claim 5 further comprising a second inverter responsive to said input signal and having an output terminal, wherein the source terminal of said p-type MOS capacitor is connected to the output terminal of said second inverter and the source terminal of said n-type MOS capacitor is connected to the output terminal of said second inverter.
Claim 10
Dependent Claim
17 words
The buffer circuit of claim 6 wherein said delay circuit comprises a plurality of inverters connected serially.
Claim 11
Dependent Claim
15 words
The buffer circuit of claim 6 wherein said delay circuit comprises three inverters connected serially.
Claim 12
Dependent Claim
104 words
A semiconductor device, comprising: a buffer circuit comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit; and a functional circuit responsive to said buffer circuit.
Claim 13
Dependent Claim
104 words
A semiconductor device, comprising: a buffer circuit comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit; and a functional circuit responsive to said buffer circuit.
Claim 14
Independent Claim
114 words
A system comprising: a processor; and a memory device in communication with said processor, slid memory device having at least one buffer circuit; said buffer circuit comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit.
Claim 15
Independent Claim
114 words
A system comprising: a processor; and a memory device in communication with said processor, slid memory device having at least one buffer circuit; said buffer circuit comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit.
Claim 16
Independent Claim
112 words
A system, comprising: a processor; and a memory device in communication with said processor, wherein said processor includes a buffer circuit, said buffer circuit comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit.
Claim 17
Independent Claim
112 words
A system, comprising: a processor; and a memory device in communication with said processor, wherein said processor includes a buffer circuit, said buffer circuit comprising: a transition delay circuit, said transition delay circuit comprising: a delay circuit having an input terminal responsive to an input signal and having an output terminal connected to a common node; a p-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an n-type MOS capacitor having a source terminal connected to said input terminal and having a gate terminal connected to said common node; and an inverter responsive to said transition delay circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |