CMOS pulse delay circuit

Claim 2

A CMOS pulse delay circuit having a capability of supplying an output signal delayed by a predetermined period from an input pulse signal, comprising: a first inverter for causing a delay, including a first p-type MOS transistor having a source to which a supply voltage is applied, a drain and a gate and a first n-type MOS transistor having a source connected to ground, a drain and a gate; voltage-controllable variable resistance elements including a second p-type MOS transistor for varying an on-resistance of said first p-type MOS transistor to control a delay amount of a trailing edge of a pulse, having a source connected to said drain of said first p-type MOS transistor, a drain and a gate to which a first control voltage is applied and a second n-type MOS transistor for varying an on-resistance of said first n-type MOS transistor to control a delay amount of a leading edge of a pulse, having a source connected to said drain of said first n-type MOS transistor, a drain connected to said drain of said second p-type MOS transistor and a gate to which a second control voltage is applied, said first control voltage applied to said gate of said second p-type MOS transistor and said second control voltage applied to said gate of said second n-type MOS transistor being independently changed for independent control of said delay amount of said trailing edge and said leading edge of pulses; a third p-type MOS transistor connected in parallel with said second p-type MOS transistor, a gate of said third p-type MOS transistor being connected to the ground; and a third n-type MOS transistor connected in parallel with said second n-type MOS transistor, a gate of said third n-type MOS transistor being connected to the supply voltage.

Claim 3

A CMOS pulse delay circuit according to claim 1, wherein said delay circuit has one input terminal connected to the gates of said first p-type and n-type MOS transistors, and a first and second control terminal connected to said gates of said second p-type and n-type MOS transistors, respectively.

Claim 4

A CMOS pulse delay circuit according to claim 2, wherein a p-type MOS capacitor is connected between said first control terminal and said one input terminal and a n-type MOS capacitor is connected between said second control terminal and said one input terminal.

Claim 5

A CMOS pulse delay circuit according to claim 1, further comprising a second inverter connected to an output of said first inverter for shaping an acute waveform.

Claim 6

A clock generating circuit having a capability of receiving a clock signal as an input and generating one or more clock signals having different phases from one another, comprising: a circuit having a plurality of CMOS pulse delay circuits connected in cascade for delaying said input clock signal by one period, each of said CMOS pulse delay circuits including: a first inverter for causing a delay, including a first p-type MOS transistor having a source to which a supply voltage is applied, a drain and a gate and a first n-type MOS transistor having a source connected to ground, a drain and a gate; and voltage-controllable variable resistance elements including a second p-type MOS transistor for varying an on-resistance of said first p-type MOS transistor to control a delay amount of a trailing edge of a pulse, having a source connected to said drain of said first p-type MOS transistor, a drain and a gate to which a first control voltage is applied and a second n-type MOS transistor for varying an on-resistance of said first n-type MOS transistor to control a delay amount of a leading edge of a pulse, having a source connected to said drain of said first n-type MOS transistor, a drain connected to said drain of said second p-type MOS transistor and a gate to which a second control voltage is applied, said first control voltage applied to said gate of said second p-type MOS transistor and said second control voltage applied to said gate of said second n-type MOS transistor being independently changed for independent control of said delay amount of said trailing edge and said leading edge of pulses; a control circuit for detecting a phase error difference between said input clock signal and a clock signal delayed for one period by said circuit, and for controlling said first and second control voltages applied to said gates of said second p-type and n-type MOS transistors, respectively, in a manner to reduce said detected phase error; a third p-type MOS transistor connected in parallel with said second p-type MOS transistor, a gate of said third p-type MOS transistor being connected to the ground; and a third n-type MOS transistor connected in parallel with said second n-type MOS transistor, a gate of said third n-type MOS transistor being connected to the supply voltage.

Claim 7

A clock generating circuit having a capability of receiving a clock signal as an input and generating one or more clock signals having different phases from one another, comprising: a circuit having a plurality of CMOS pulse delay circuits connected in cascade for delaying said input clock signal by one period, each of said CMOS pulse delay circuits including: a first inverter for causing a delay, including a first p-type MOS transistor having a source to which a supply voltage is applied, a drain and a gate and a first n-type MOS transistor having a source connected to ground, a drain and a gate; and voltage-controllable variable resistance elements including a second p-type MOS transistor for varying an on-resistance of said first p-type MOS transistor to control a delay amount of a trailing edge of a pulse, having a source connected to said drain of said first p-type MOS transistor, a drain and a gate to which a first control voltage is applied and a second n-type MOS transistor for varying an on-resistance of said first n-type MOS transistor to control a delay amount of a leading edge of a pulse, having a source connected to said drain of said first n-type MOS transistor, a drain connected to said drain of said second p-type MOS transistor and a gate to which a second control voltage is applied, said first control voltage applied to said gate of said second p-type MOS transistor and said second control voltage applied to said gate of said second n-type MOS transistor being independently changed for independent control of said delay amount of said trailing edge and said leading edge of pulses; a control circuit for detecting a phase error difference between said input clock signal and a clock signal delayed for one period by said circuit, and for controlling said first and second control voltages applied to said gates of said second p-type and n-type MOS transistors, respectively, in a manner to reduce said detected phase error; a third p-type MOS transistor connected in parallel with said second p-type MOS transistor, a gate of said third p-type MOS transistor being connected to the ground; and a third n-type MOS transistor connected in parallel with said second n-type MOS transistor, a gate of said third n-type MOS transistor being connected to the supply voltage.

Claim 8

A clock generating circuit according to claim 5, wherein each CMOS pulse delay circuit has one input terminal connected to the gates of said first p-type and n-type MOS transistors, and a first and second control terminal connected to said gates of said second p-type and n-type MOS transistors, respectively.

Claim 9

A clock generating circuit according to claim 6, wherein said control circuit has a first output connected to said first control terminal of each CMOS pulse delay circuit and a second output connected to said second control terminal of each CMOS pulse delay circuit.

Claim 10

A clock generating circuit according to claim 7, wherein said control circuit includes means for detecting said phase error between said input clock signal and the delayed clock signal, means for determining as to whether a delay error is on said trailing edge or on said leading edge of a pulse to select one of said first and second outputs, and means for generating a pulse having a pulse width according to a delay amount.

Claim 11

A clock generating circuit according to claim 8, wherein said pulse generating means generates a positive pulse when a delay on the trailing edge of a pulse is larger than one clock period and generates a negative pulse when a delay on the trailing edge of a pulse is smaller than one clock period.

Claim 12

A clock generating circuit according to claim 9, wherein said pulse generating means generates a negative pulse when a delay on the leading edge of a pulse is larger than one clock period and generates a positive pulse when a delay on the leading edge of a pulse is smaller than one clock period.