Abstract Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
A soft wakeup output buffer comprising: a buffer (21) for generating a corresponding output signal (to I/O pad 23) from an input signal (36); means (T) responsive to a high impedance control signal (A) for placing said buffer into a high impedance mode; means (FS) responsive to a slew rate signal (D) for controlling response rate of said buffer; and means (229) responsive to said high impedance control signal for controlling said slew rate signal (D) comprising: a logic gate (U3) having two inputs which generates said slew rate signal (D); means for generating a first slew rate control signal and providing said first slew rate control signal to a first input of said logic gate; and means for generating a second slew rate control signal which receives said high impedance control signal (A); and applies a delay of time Td to said high impedance control signal (A) and after time Td applies said high impedance control signal (A) to a second input of said logic gate (U3).
Claim 2
Dependent Claim
168 words
A soft wakeup output buffer comprising: a buffer (21) for generating a corresponding output signal (to I/O pad 23) from an input signal (36); means (T) responsive to a high impedance control signal (A) for placing said buffer into a high impedance mode; means (FS) responsive to a slew rate signal (D) for controlling response rate of said buffer; and means (229) responsive to said high impedance control signal for controlling said slew rate signal (D) comprising: a logic gate (U3) having two inputs which generates said slew rate signal (D); means for generating a first slew rate control signal and providing said first slew rate control signal to a first input of said logic gate; and means for generating a second slew rate control signal which receives said high impedance control signal (A); and applies a delay of time Td to said high impedance control signal (A) and after time Td applies said high impedance control signal (A) to a second input of said logic gate (U3).