US6043677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable clock manager for a programmable logic device that can implement delay-locked loop functions
Assignee: Lattice Semiconductor Corp
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Filing: 1997-10-15
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Granted: 2000-03-28
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Expires: 2017-10-15
Abstract
Abstract A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.
Inventors
- 👤 Lucian R. Albu
- 👤 Barry K. Britton
- 👤 Wai-Bor Leung
- 👤 Richard G. Stuby, Jr.
- 👤 James A. Thompson
- 👤 Zeljko Zilic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1774; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
55 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), wherein the PCM comprises delay-locked loop (DLL) circuitry adapted to convert an input clock into at least one output clock and the DLL circuitry is adapted to perform one or more DLL functions using a tapped delay line configured with combinatorial logic.
Claim 2
Dependent Claim
55 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), wherein the PCM comprises delay-locked loop (DLL) circuitry adapted to convert an input clock into at least one output clock and the DLL circuitry is adapted to perform one or more DLL functions using a tapped delay line configured with combinatorial logic.
Claim 3
Dependent Claim
15 words
The invention of claim 1, wherein the PLD is a field programmable gate array (FPGA).
Claim 4
Dependent Claim
18 words
The invention of claim 1, wherein at least one of the DLL functions is a duty-cycle adjustment function.
Claim 5
Dependent Claim
30 words
The invention of claim 3, wherein the duty-cycle adjustment function is adapted to adjust the duty cycle of the output clock based on a percentage of an input clock period.
Claim 6
Dependent Claim
17 words
The invention of claim 3, wherein at least one of the DLL functions is a clock-doubling function.
Claim 7
Dependent Claim
32 words
The invention of claim 5, wherein the duty-cycle adjustment function is adapted to be combined with the clock-doubling function, such that the duty cycle of each doubled clock cycle is independently adjusted.
Claim 8
Dependent Claim
18 words
The invention of claim 3, wherein at least one of the DLL functions is a clock multiplication function.
Claim 9
Dependent Claim
26 words
The invention of claim 1, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.
Claim 10
Dependent Claim
54 words
The invention of claim 1, wherein the PCM is adapted to be used as a system component independent of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |