Clock frequency multiplying and squaring circuit and method

Claim 2

A circuit for generating an output signal having a frequency that is a multiple of an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, said delay means being comprised of a plurality of serially connected delay elements wherein a first delay element has an input connected to said input clock signal and wherein an output of each of said plurality of serially connected delay elements is connected to one of said output ports, individual ones of said plurality of output ports outputting a signal that preserves a waveform shape of the input clock signal and that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and combinatorial logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal without storing said input clock signal and without storing any of said signals emanating from said output ports, said combinatorial logic means having an output port for outputting a signal having a frequency that is a multiple of a frequency of the input clock signal and that is synchronous therewith.

Claim 3

A circuit as set forth in claim 1 wherein said delay means is comprised of: a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes.

Claim 4

A circuit as set forth in claim 2 wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough.

Claim 5

A circuit as set forth in claim 1 wherein the signal that is output from said output port of said logic means has a 50% duty cycle.

Claim 6

A circuit for generating an output signal having a frequency that is a multiple of an input clock signal, comprising: delay means having an input port and a plurality of output port, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a frequency that is a multiple of a frequency of the input clock signal and that is synchronous therewith; wherein said delay means is comprised of a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes; wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough; and wherein the delay is equal to approximately 25% of the period of the input clock signal.

Claim 7

A circuit for generating an output signal having a frequency that is a multiple of an input clock signal, comprising: delay means having an input port and a plurality of output port, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a frequency that is a multiple of a frequency of the input clock signal and that is synchronous therewith; wherein said delay means is comprised of a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes; wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough; and wherein the delay is equal to approximately 25% of the period of the input clock signal.

Claim 8

A circuit for generating an output signal having a frequency that is a multiple of an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a frequency that is a multiple of a frequency of the input clock signal and that is synchronous therewith; wherein said delay means is comprised of a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes; wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough; wherein the signal that is output from said output port of said logic means has a 50% duty cycle; and wherein the duty cycle of the input clock signal is other than 50%.

Claim 9

A circuit for generating an output signal having a frequency that is a multiple of an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a frequency that is a multiple of a frequency of the input clock signal and that is synchronous therewith; wherein said delay means is comprised of a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes; wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough; wherein the signal that is output from said output port of said logic means has a 50% duty cycle; and wherein the duty cycle of the input clock signal is other than 50%.

Claim 10

A circuit for generating an output signal from an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, said delay means being comprised of a plurality of serially connected delay elements wherein a first delay element has an input connected to said input clock signal and wherein an output of each of said plurality of serially connected delay elements is connected to one of said output ports, individual ones of said plurality of output ports outputting a signal that preserves a waveform shape of the input clock signal and that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and combinatorial logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal, said combinatorial logic means having an output port for outputting an output signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein said input clock signal has a duty cycle of other than 50%.

Claim 11

A circuit for generating an output signal from an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, said delay means being comprised of a plurality of serially connected delay elements wherein a first delay element has an input connected to said input clock signal and wherein an output of each of said plurality of serially connected delay elements is connected to one of said output ports, individual ones of said plurality of output ports outputting a signal that preserves a waveform shape of the input clock signal and that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and combinatorial logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal, said combinatorial logic means having an output port for outputting an output signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein said input clock signal has a duty cycle of other than 50%.

Claim 12

A circuit as set forth in claim 7 wherein the signal that is output from said output port has a frequency that is a multiple of the frequency of the input clock signal.

Claim 13

A circuit for generating an output signal from an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and combinatorial logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal, said combinatorial logic means having an output port for outputting an output signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein said input clock signal has a duty cycle of other than 50%, and wherein said delay means is comprised of: a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes.

Claim 14

A circuit for generating an output signal from an input clock signal, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and combinatorial logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said combinatorial logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal, said combinatorial logic means having an output port for outputting an output signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein said input clock signal has a duty cycle of other than 50%, and wherein said delay means is comprised of: a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes.

Claim 15

A circuit as set forth in claim 9 wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough.

Claim 16

A circuit for generating an output signal having a 50% duty cycle from an input clock signal having a duty cycle of other than 50%, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein said delay means is comprised of a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes; wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough; and wherein the delay is equal to approximately 25% of the period of the input clock signal.

Claim 17

A circuit for generating an output signal having a 50% duty cycle from an input clock signal having a duty cycle of other than 50%, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein said delay means is comprised of a first delay element means having an input for coupling to the input clock signal and an output coupled to a first one of said plurality of output nodes; a second delay element means having an input coupled to said output of said first delay element means and an output coupled to a second one of said plurality of output nodes; and a third delay element means having an input coupled to said output of said second delay element means and an output coupled to a third one of said plurality of output nodes; wherein each of said delay element means introduces an equal amount of delay to a signal propagating therethrough; and wherein the delay is equal to approximately 25% of the period of the input clock signal.

Claim 18

A circuit for generating an output signal having a 50% duty cycle from an input clock signal having a duty cycle of other than 50%, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein the signal that is output from said output port has a frequency that is equal to the frequency of the input clock signal.

Claim 19

A circuit for generating an output signal having a 50% duty cycle from an input clock signal having a duty cycle of other than 50%, comprising: delay means having an input port and a plurality of output ports, said input port for coupling to the input clock signal, individual ones of said plurality of output ports outputting a signal that is delayed with respect to the input clock signal and also with respect to others of said plurality of output ports; and logic means having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to said plurality of output ports, said logic means operating to logically combine signals emanating from said plurality of output ports with the input clock signal and having an output port for outputting a signal having a 50% duty cycle and that is synchronous with the input clock signal; wherein the signal that is output from said output port has a frequency that is equal to the frequency of the input clock signal.

Claim 22

A method as set forth in claim 13 wherein the step of logically combining further generates the output clock signal to have a symmetrical waveform.

Claim 23

A method as set forth in claim 13 wherein the step of logically combining further generates the output clock signal to be in synchronism with the input clock signal.

Claim 26

A method as set forth in claim 16 wherein the step of logically combining further generates the first and the second output clock signals to be in synchronism with the input clock signal.