US5666322A
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Phase-locked loop timing controller in an integrated circuit memory
Assignee: NEC Electronics America Inc
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Filing: 1995-09-21
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Granted: 1997-09-09
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Expires: 2015-09-21
Abstract
Abstract Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.
Inventors
- 👤 Cecil W. Conkle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:16
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G11C7/10; G11C7/1015; G11C7/1042; G11C7/1072
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
82 words
An integrated circuit memory comprising: memory array; and a timing circuit coupled to the memory array via an internal clock line and coupled to an external signal clock line, the timing circuit including: a clock multiplier and clock edge synchronizing circuit having an input terminal coupled to the external signal clock line and having an output terminal coupled to the internal clock line, wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line.
Claim 2
Dependent Claim
82 words
An integrated circuit memory comprising: memory array; and a timing circuit coupled to the memory array via an internal clock line and coupled to an external signal clock line, the timing circuit including: a clock multiplier and clock edge synchronizing circuit having an input terminal coupled to the external signal clock line and having an output terminal coupled to the internal clock line, wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line.
Claim 3
Dependent Claim
73 words
A memory according to claim 1 further comprising: an inpututput circuit coupled to the memory array by a plurality of internal data lines; a decoding circuit coupled to the memory array and the input/output circuit by a plurality of decoded address lines; and a control circuit coupled to the input/output circuit by a control line and coupled to the internal clock line; wherein the timing circuit is coupled to the internal clock line.
Claim 4
Dependent Claim
25 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit includes a phase-locked loop circuit configurable to furnish frequency multiplication.
Claim 5
Dependent Claim
25 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit includes a delay-locked loop circuit configurable to furnish frequency multiplication.
Claim 6
Dependent Claim
32 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line by N where N is an integer.
Claim 7
Dependent Claim
19 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit includes a clock doubler.
Claim 8
Dependent Claim
19 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit includes a clock tripler.
Claim 9
Dependent Claim
19 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit includes a clock quadrupler.
Claim 10
Dependent Claim
38 words
A memory according to claim 1 wherein the clock multiplier and clock edge synchronizing circuit generates a plurality of internal timing signals on the internal clock line for each external clock signal on the external signal clock line.
Claim 11
Dependent Claim
15 words
A memory according to claim 1 wherein the memory array includes a static RAM memory.
Claim 12
Dependent Claim
15 words
A memory according to claim 1 wherein the memory array includes a video RAM memory.
Claim 13
Dependent Claim
15 words
A memory according to claim 1 wherein the memory array includes a dynamic RAM memory.
Claim 14
Dependent Claim
15 words
A memory according to claim 1 wherein the memory array includes a dynamic ROM memory.
Claim 15
Dependent Claim
15 words
A memory according to claim 1 wherein the memory array includes a static ROM memory.
Claim 16
Dependent Claim
14 words
A memory according to claim 1 wherein the memory array includes a RAMDAC circuit.
Claim 17
Dependent Claim
123 words
A computer system comprising: a memory controller; a data bus coupled to the memory controller; and a plurality of memory banks coupled to the data bus and mutually sharing data bus access, each of the plurality of memory banks being an integrated circuit memory including: a memory array; and a timing circuit coupled to the memory array via an internal clock line and coupled to an external signal clock line, the timing circuit including: a clock multiplier and clock edge synchronizing circuit having an input terminal coupled to the external signal clock line and having an output terminal coupled to the internal clock line, wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line.
Claim 18
Dependent Claim
123 words
A computer system comprising: a memory controller; a data bus coupled to the memory controller; and a plurality of memory banks coupled to the data bus and mutually sharing data bus access, each of the plurality of memory banks being an integrated circuit memory including: a memory array; and a timing circuit coupled to the memory array via an internal clock line and coupled to an external signal clock line, the timing circuit including: a clock multiplier and clock edge synchronizing circuit having an input terminal coupled to the external signal clock line and having an output terminal coupled to the internal clock line, wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line.
Claim 19
Dependent Claim
73 words
A computer system according to claim 16 further comprising: an input/output circuit coupled to the memory by a plurality of internal data lines; a decoding circuit coupled to the memory array and the input/output circuit by a plurality of decoded address lines; and a control circuit coupled to the input/output circuit by a control line and coupled to the internal clock line; wherein the timing circuit is coupled to the internal clock line.
Claim 20
Independent Claim
72 words
A method of operating a plurality of memory banks comprising the steps of: receiving a clock signal at a clock frequency; multiplying the clock frequency to generate multiple clock edges; timing a plurality of phases of the clock signal with the clock edges; synchronizing timing of the multiple clock edges; and driving a plurality of memory banks, each memory bank being driven with selected individual clock edge of the multiple clock edges.
Claim 21
Independent Claim
72 words
A method of operating a plurality of memory banks comprising the steps of: receiving a clock signal at a clock frequency; multiplying the clock frequency to generate multiple clock edges; timing a plurality of phases of the clock signal with the clock edges; synchronizing timing of the multiple clock edges; and driving a plurality of memory banks, each memory bank being driven with selected individual clock edge of the multiple clock edges.
Claim 22
Dependent Claim
19 words
A method according to claim 18 wherein the synchronizing step includes synchronizing clock edges using a phase-locked loop circuit.
Claim 23
Dependent Claim
19 words
A method according to claim 18 wherein the synchronizing step includes synchronizing clock edges using a delay-locked loop circuit.
Claim 24
Dependent Claim
25 words
A method according to claim 18 wherein the clock frequency multiplying step includes a step of multiplying the frequency by N where is an integer.
Claim 25
Dependent Claim
19 words
A method according to claim 18 wherein the clock frequency multiplying step includes a step of doubling the frequency.
Claim 26
Dependent Claim
19 words
A method according to claim 18 wherein the clock frequency multiplying step includes a step of tripling the frequency.
Claim 27
Dependent Claim
19 words
A method according to claim 18 wherein the clock frequency multiplying step includes a step of quadrupling the frequency.
Claim 28
Dependent Claim
17 words
A memory according to claim 1 where the timing signal is an enable signal from a processor.
Claim 29
Dependent Claim
18 words
A memory according to claim 1 where the timing signal is a clock signal from a clock circuit.
Claim 30
Dependent Claim
18 words
A memory according to claim 16 where the timing signal is an enable signal from the memory controller.
Claim 31
Dependent Claim
18 words
A memory according to claim 16 where the timing signal is a clock signal from a clock circuit.
Claim 32
Dependent Claim
15 words
A method according to claim 18 wherein the clock signal is produced by a processor.
Claim 33
Dependent Claim
16 words
A method according to claim 18 wherein the clock signal is produced by a clock circuit.
Claim 34
Dependent Claim
35 words
The method of claim 18 further comprising accessing one of the plurality of memory banks by a processor when the one of the plurality of memory banks is being driven with selected individual clock edges.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |