US5475718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital phase-locked loop
Assignee: Nokia of America Corp
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Filing: 1994-02-07
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Granted: 1995-12-12
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Expires: 2014-02-07
Abstract
Abstract A digital phase-locked loop includes a digital controller whose output is coupled to a controllable oscillator and which loop comprises a phase detector (PD) whose two inputs are provided to receive a pulse-shaped reference signal (REF) and a pulse-shaped oscillator signal (OSC) generated by the oscillator. This phase detector comprises a first circuit branch provided to receive the reference and the oscillator signal, to form a pulse-shaped signal whose pulse width is equal to the distance in time between two specific successive pulse edges of the reference and oscillator signal, to filter by low-pass filter the pulse-shaped signal and to code sample values of the low-pass filtered signal with a first number (Nf) of least significant bits. This phase detector comprises a second circuit branch, coupled to the first circuit branch, which second branch comprises a counter means which changes its count if no or more than one specific edge of the oscillator signal occur(s) between two successive given edges of the reference signal, which codes the result of the counting with a second number (Ng) of most significant bits.
Inventors
- 👤 Werner Rosenkranz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:26
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
152 words
Digital phase-locked loop comprising a controller whose output is coupled to a controllable oscillator, a phase detector whose two inputs are arranged for receiving a reference signal and an oscillator signal that is generated by the oscillator, said phase detector comprising: a first circuit branch for deriving a first value from the time difference between reference points of the reference and oscillator signals of the phase detector; and a second circuit branch which includes a counter device for detecting a difference between a number of reference points of the reference signal and a number of reference points of the oscillator signal which have been detected from a reference instant (t=0) onwards, to form a second value; combining means being provided for combining the first and second values to generate a combined value, the combined value being provided to an input of said controller, and the output of said controller controlling the oscillator.
Claim 2
Dependent Claim
152 words
Digital phase-locked loop comprising a controller whose output is coupled to a controllable oscillator, a phase detector whose two inputs are arranged for receiving a reference signal and an oscillator signal that is generated by the oscillator, said phase detector comprising: a first circuit branch for deriving a first value from the time difference between reference points of the reference and oscillator signals of the phase detector; and a second circuit branch which includes a counter device for detecting a difference between a number of reference points of the reference signal and a number of reference points of the oscillator signal which have been detected from a reference instant (t=0) onwards, to form a second value; combining means being provided for combining the first and second values to generate a combined value, the combined value being provided to an input of said controller, and the output of said controller controlling the oscillator.
Claim 3
Dependent Claim
106 words
Digital phase-locked loop as claimed in claim 1, characterized in that the first circuit branch is provided for: receiving the reference and oscillator signals, said reference and oscillator signals being pulse shaped; forming a pulse-shaped signal whose pulse widths are derived from the distance in time between two given successive pulse edges of said reference and oscillator signals used as reference points; low-pass filtering the pulse-shaped signal; and coding samples values of the low-pass filtered signal with a first number of least significant bits; and in that the second circuit branch is provided for coding the second value with a second number of most significant bits.
Claim 4
Dependent Claim
34 words
Digital phase-locked loop as claimed in claim 1, characterized in that the counter means in the second circuit branch comprises an up/down-counter having inputs at which the reference and the oscillator signals are present.
Claim 5
Dependent Claim
88 words
Digital phase-locked loop as claimed in claim 1, characterized in that the input of the second circuit branch of the phase detector is arranged for receiving a signal of the first circuit branch, in that a differentiator comprising a high-pass filter is arranged at the second circuit branch for receiving said signal of the first circuit branch, in that a threshold detector is coupled to the output of the differentiator comprising the high-pass filter and in that an up/down-counter is coupled to the output of the threshold detector.
Claim 6
Dependent Claim
92 words
Digital phase-locked loop as claimed in claim 1, characterized in that the second circuit branch of the phase detector is coupled to the output of the first circuit branch, in that the second circuit branch is located in a digital section of the digital phase-locked loop, in that the second circuit branch comprises means for producing a difference between two successive phase difference sample values, in that this difference is applied to a threshold detector and in that an accumulator means is provided for integrating the output values of the threshold detector.
Claim 7
Dependent Claim
32 words
Digital phase-locked loop as claimed in claim 5 characterized in that the digital section of the phase-locked loop comprises means for processing the phase difference sample values accordance with a non-linear characteristic.
Claim 8
Dependent Claim
29 words
Digital phase-locked loop as claimed in claim 1, characterized in that a number of most significant bits generated in the second circuit branch are multiplied by a weight factor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-11 | 1999-06-12 | 1999-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-11 | 2003-06-12 | 2003-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-11 | 2007-06-12 | 2007-12-12 | $7700.00 | Window Closed / Lapsed |