US6628154B2
Expired / Lapsed
US
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Digitally controlled analog delay locked loop (DLL)
Assignee: Monterey Research LLC
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Filing: 2001-07-31
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Granted: 2003-09-30
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Expires: 2021-07-31
Abstract
Abstract An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.
Inventors
- 👤 Timothy E. Fiscus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:35
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818; H03L7/085; H03L7/087; H03K2005/00013; H03K2005/00019; H03K2005/00026; H03K2005/0015; H03K2005/00195; H03K2005/00208; H03K2005/00234; H03K2005/00241
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
117 words
An apparatus comprising: an analog delay line (i) comprising (a) a delay chain comprising a plurality of delay elements each comprising a plurality of delay cells and amplifiers and (b) a shift register and (ii) configured to generate an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjustable with respect to said input signal in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal; and a control circuit configured to generate said first and said second control signals in response to said input signal and said output signal.
Claim 2
Independent Claim
117 words
An apparatus comprising: an analog delay line (i) comprising (a) a delay chain comprising a plurality of delay elements each comprising a plurality of delay cells and amplifiers and (b) a shift register and (ii) configured to generate an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjustable with respect to said input signal in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal; and a control circuit configured to generate said first and said second control signals in response to said input signal and said output signal.
Claim 3
Dependent Claim
17 words
The apparatus according to claim 1 , wherein said shift register comprises a plurality of register elements.
Claim 4
Dependent Claim
16 words
The apparatus according to claim 2 , wherein each of said register elements comprises a flip-flop.
Claim 5
Dependent Claim
20 words
The apparatus according to claim 1 , wherein each of said delay elements comprises one or more differential CMOS amplifiers.
Claim 6
Dependent Claim
29 words
The apparatus according to claim 1 , wherein each of said delay elements comprises one or more differential amplifiers with a diode load in parallel with a voltage-controlled load.
Claim 7
Dependent Claim
55 words
The apparatus according to claim 1 , wherein said control circuit comprises: a phase detector circuit configured to generate said first and second control signals in response to said input signal and a feedback signal; and a delay circuit configured to generate said feedback signal in response to said output signal and a predetermined delay.
Claim 8
Dependent Claim
88 words
The apparatus according to claim 6 , wherein said phase detector circuit comprises: a first phase detector circuit configured to generate said first control signal in response to said input signal and said feedback signal, wherein said first control signal is configured to adjust said phase in discrete amounts; and a second phase detector circuit configured to generate said second control signal in response to said input signal and said feedback signal, wherein said second control signal is configured to adjust said phase continuously within a predetermined range.
Claim 9
Dependent Claim
39 words
The apparatus according to claim 7 , wherein said first phase detector circuit comprises a digital control circuit configured to control said analog delay line in response to a phase difference between said input signal and said feedback signal.
Claim 10
Dependent Claim
41 words
The apparatus according to claim 7 , wherein said second phase detector circuit comprises a charge pump and loop filter configured to control said analog delay line in response to a phase difference between said input signal and said feedback signal.
Claim 11
Independent Claim
106 words
An apparatus comprising: means for generating an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjusted with respect to said input signal by selecting a number of delay elements in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal; means for generating said first and said second control signals in response to said input signal and said output signal; and means for controlling a presentation of data by a memory device in response to said output signal.
Claim 12
Independent Claim
106 words
An apparatus comprising: means for generating an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjusted with respect to said input signal by selecting a number of delay elements in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal; means for generating said first and said second control signals in response to said input signal and said output signal; and means for controlling a presentation of data by a memory device in response to said output signal.
Claim 13
Independent Claim
123 words
A method for locking and adjusting a phase of an output signal to a phase of an input signal comprising the steps of: (A) generating an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjusted with respect to said input signal by selecting a number of delay elements in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal; (B) generating said first and said second control signals in response to said input signal and said output signal; and (C) controlling a presentation of data by a memory device in response to said output signal.
Claim 14
Independent Claim
123 words
A method for locking and adjusting a phase of an output signal to a phase of an input signal comprising the steps of: (A) generating an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjusted with respect to said input signal by selecting a number of delay elements in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal; (B) generating said first and said second control signals in response to said input signal and said output signal; and (C) controlling a presentation of data by a memory device in response to said output signal.
Claim 15
Dependent Claim
17 words
The method according to claim 11 , wherein said first control signal comprises a digital control signal.
Claim 16
Dependent Claim
17 words
The method according to claim 11 , wherein said second control signal comprises an analog control signal.
Claim 17
Dependent Claim
36 words
The method according to claim 13 , wherein the step (A) comprises the sub-step of: controlling an amount of delay generated by each of said number of delay elements in response to said analog control signal.
Claim 18
Dependent Claim
31 words
The apparatus according to claim 1 , wherein said plurality of delay elements are each configured to provide a delay that is continuously adjustable in response to said second control signal.
Claim 19
Dependent Claim
27 words
The apparatus according to claim 1 , wherein said first control signal comprises a digital control signal and said second control signal comprises an analog control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-09-29 | 2007-03-31 | 2007-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-29 | 2011-03-31 | 2011-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-29 | 2015-03-31 | 2015-09-30 | $7700.00 | Window Closed / Lapsed |