Clock latency compensation circuit for DDR timing

Claim 1

A clock to data latency compensation circuit which includes a delay locked loop, for a system associated with at least one integrated circuit, comprising: a receiver, comprising at least one monostable multivibrator circuit, operable to receive a system clock signal and to produce first and second receiver clock signals; a first delay line, including an input and an output, comprising active impedance circuitry, said first delay line receiving said second receiver clock signal; a second delay line, including an input and an output, comprising active impedance circuitry, said second delay line receiving said first receiver first clock signal; a delay element, including an input and an output, which introduces phase delay to said delay locked loop which is operable to receive the output from said second delay line; a phase comparator operable to compare the phase of said delay element output and said first receiver clock signal, and to produce a control signal to control the delay produced by said first and second delay lines; a logic gate operable to receive the signals output from said first and second delay lines; and a driver circuit operable to receive ouput from said logic gate to drive output for said clock to data latency compensation circuit.