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EP0949760A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Pulse delay circuit with variable delay time

Assignee: Sanyo Electric Co Ltd
•
Filing: 1999-03-25
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Granted: —
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Expires: 2019-03-25
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Abstract

Abstract A pulse delay circuit includes a voltage-controlled oscillator (VCO) (4), a phase comparator (7), a low pass filter (8) and a delay line (2). The VCO (4) includes a plurality of first delay elements (50, 51) connected in a loop shape and generates an oscillation output signal according to a control voltage. The phase comparator (7) receives the oscillation output signal and a reference signal, compares the phase of the oscillation output signal and the phase of the reference signal, and generates a comparison signal indicating a phase difference therebetween. The low pass filter (8) receives the comparison signal and generates the control voltage. The delay line (2) includes a plurality of series connected second delay elements (60) for delaying a clock signal and generating a plurality of delay clock signals. Each of the second delay elements (60) is substantially identical to the first delay elements (50, 51). Each of the first and second delay elements (50, 51, 60) sets its own delay time in accordance with the control voltage.

Inventors

  • 👤 Masashi Kiyose
  • 👤 Toru Akiyama

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 08:07
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/14; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K5/133; H03L7/081; H03L7/099; H03L7/0995

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 173 words
A pulse delay circuit characterized by: a voltage-controlled oscillator (VCO) (4) including a plurality of first delay elements (50, 51) connected in a ring shape and generating an oscillation output signal according to a control voltage; a phase comparator (7) for receiving a reference signal one of the oscillation output signal and a frequency-divided oscillation output signal, comparing the phase of the reference signal and the phase of one of the oscillation output signal and the frequency-divided oscillation output signal, and generating a comparison signal indicating a phase difference therebetween; a low pass filter (8) for receiving the comparison signal and generating the control voltage; and a delay line (2) including a plurality of series connected second delay elements (60) for delaying a clock signal and generating a plurality of delay clock signals, each of the second delay elements (60) being substantially identical to the first delay elements (50, 51), wherein each of the first and second delay elements (50, 51, 60) sets its own delay time in accordance with the control voltage.
Claim 2
Dependent Claim 32 words
The circuit of claim 1, wherein each of the first and second delay elements (50, 51, 60) includes a transistor for controlling a current flowing therethrough in accordance with the control voltage.
Claim 3
Dependent Claim 39 words
The circuit of claim 1, wherein the delay line (2) includes a selector connected to the plurality of second delay elements (60), for selecting one of the plurality of delay clock signals in accordance with an associated selection signal.
Claim 4
Dependent Claim 22 words
The circuit of claim 1, wherein each of the plurality of first and second delay elements is an inverter (50, 51, 60).
Claim 5
Dependent Claim 27 words
The circuit of claim 4, wherein each of the inverters operates by receiving a predetermined bias voltage and the control voltage from the low pass filter (8).
Claim 6
Dependent Claim 22 words
The circuit of claim 1, wherein each of the plurality of first and second delay elements (50, 51, 60) is a comparator.

References Cited (Backward Citations)

EP0087707A2 Cited
US4703251A Cited
EP0395118A1 Cited
EP0306662A2 Cited
US5428309A Cited
US5677650A Cited

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