EP0087707A2
Expired / Lapsed
EP
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Pulse delay circuit
Assignee: HP Inc
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Filing: 1983-02-21
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Granted: —
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Expires: 2003-02-21
Abstract
Abstract A pulse delay circuit uses a cascaded series of inverting elements with input thresholds to delay the transitions of an input pulse as it progresses through the series. The output of each inverter charges a capacitance in one polarity, but cannot discharge it. The discharge is achieved by current sources connected to the capacitors, charging them in a direction opposite to that of the inverter outputs. This produces a ramp which subsequently produces an abrupt transition aslhe ramp eventually crosses the input threshold. In this way every other inverter delays the leading edge, while the alternate intervening inverters delay the trailing edge. A final capacitance-tolerant inverting element with a threshold produces abrupt transitions for each transition as its input, to create a delayed replica of the input pulse. Asymmetries in the relative delay of the leading and trailing edges are corrected either by independently controlling one of the current sources or one of the thresholds.
Inventors
- 👤 Phillip Kent Hardage
- 👤 Stephen W. Peurifoy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 10:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
347 words
A pulse delay circuit characterized by first inverter means (2, 10) having an input for receiving an input pulse to be delayed and having an output for delivering in response to input pulse transitions of a first polarity crossing an input threshold an output signal through a low internal impedance that readily conducts current and fordelivering in response to input pulse transitions of an opposite polarity re-crossing the input threshold a substantially higher internal impedance that essentially does not conduct current; first capacitance means (5, 12) connected between outputs of the first inverter means and an AC ground; first current source means (7, 14) connected to the outputs of the first inverter means for supplying a current to the first capacitance means that charges that capacitance means in a direction opposite to that caused by input pulse transitions of the first polarity; second inverter means (3, 11) having inputs coupled to outputs of the first inverter means and having an output delivering in response to a signal transition of the first polarity crossing an input threshold an output signal through a low internal impedance that readily conducts current and for producing at its output in response to a signal transition of the opposite polarity re-crossing the input threshold a substantially higher internal impedance that essentially does not conduct current; second capacitance means (6, 13) connected between the output of the second inverter means and an AC ground; second current source means (8, 15) connected to the output of the inverter means, for supplying a current to the second capacitance means that charges that capacitance means in a direction opposite to that caused by signal transitions of the first polarity; and output circuit means (4) having an input coupled to the output of the second inverter means, for delivering at its output in response to transitions of either polarity upon its input that cross a threshold an abruptly transitioning output signal whose leading and trailing edges are each delayed from the corresponding leading and trailing edges of the pulse applied to the input of the first inverter means.
Claim 2
Dependent Claim
347 words
A pulse delay circuit characterized by first inverter means (2, 10) having an input for receiving an input pulse to be delayed and having an output for delivering in response to input pulse transitions of a first polarity crossing an input threshold an output signal through a low internal impedance that readily conducts current and fordelivering in response to input pulse transitions of an opposite polarity re-crossing the input threshold a substantially higher internal impedance that essentially does not conduct current; first capacitance means (5, 12) connected between outputs of the first inverter means and an AC ground; first current source means (7, 14) connected to the outputs of the first inverter means for supplying a current to the first capacitance means that charges that capacitance means in a direction opposite to that caused by input pulse transitions of the first polarity; second inverter means (3, 11) having inputs coupled to outputs of the first inverter means and having an output delivering in response to a signal transition of the first polarity crossing an input threshold an output signal through a low internal impedance that readily conducts current and for producing at its output in response to a signal transition of the opposite polarity re-crossing the input threshold a substantially higher internal impedance that essentially does not conduct current; second capacitance means (6, 13) connected between the output of the second inverter means and an AC ground; second current source means (8, 15) connected to the output of the inverter means, for supplying a current to the second capacitance means that charges that capacitance means in a direction opposite to that caused by signal transitions of the first polarity; and output circuit means (4) having an input coupled to the output of the second inverter means, for delivering at its output in response to transitions of either polarity upon its input that cross a threshold an abruptly transitioning output signal whose leading and trailing edges are each delayed from the corresponding leading and trailing edges of the pulse applied to the input of the first inverter means.
Claim 3
Dependent Claim
26 words
A pulse delay circuit as in claim 1 wherein the currents supplied by the first (7, 14) and second (8, 15) current sources are independently variable.
Claim 4
Dependent Claim
26 words
A pulse delay circuit as in claim 1 or claim 2 wherein the first (2, 10) and second (3, 11) inverter means possesses emitter follower outputs.
Claim 5
Dependent Claim
35 words
A plurality of pulse delay circuits as in claim 3 fabricated within an integrated circuit and incorporating means to vary as a function of temperature the currents supplied by the first and second current sources.
Claim 6
Dependent Claim
28 words
Application of the pulse delay circuit of claim 1 or claim 2 to introduce delay into the acquisition of state-data with respect to the acquisition of clock data.
References Cited (Backward Citations)
No citation records indexed.
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