US6476652B1
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Delay locked loop for use in synchronous dynamic random access memory
Assignee: SK Hynix Inc
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Filing: 2000-10-31
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Granted: 2002-11-05
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Expires: 2020-10-31
Abstract
Abstract A delay locked loop (DLL) is used to compensate for a skew in a synchronous dynamic random access memory. The delay locked loop includes: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation unit, in response to the external clock signal and the delayed clock signal, for generating control signals; a first delay unit, in response to the control signals, for delaying the delayed control signal to generate a first DLL clock signal, wherein the first delay unit has a large unit delay; and a second delay unit, in response to the control signals, for delaying the first DLL clock signal to generate a second DLL clock signal, wherein the second delay means in a small unit delay.
Inventors
- 👤 Seong-Hoon Lee
- 👤 Jung-Il Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
232 words
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model for delaying an external clock signal to generate a delayed clock signal; a signal generation means, responsive to the external clock signal and the delayed clock signal, for generating control signals, an internal clock signal, and a delayed internal clock signal; a first delay means, responsive to the control signals, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means has a first amount of delay time; and a second delay means, responsive to the control signals, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has a second amount of delay time, the second amount of delay time being shorter than the first amount of delay time, wherein the signal generating means includes: a control means, response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signals include a shift signal, a replication signal and a replication enable signal; a first oscillation means, responsive to the internal clock signal and the delayed internal clock signal, for generating a measurement oscillating signal; and a second oscillation means, responsive to the replication signal and the replication enable signal, for generating a replication oscillating signal.
Claim 2
Dependent Claim
232 words
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model for delaying an external clock signal to generate a delayed clock signal; a signal generation means, responsive to the external clock signal and the delayed clock signal, for generating control signals, an internal clock signal, and a delayed internal clock signal; a first delay means, responsive to the control signals, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means has a first amount of delay time; and a second delay means, responsive to the control signals, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has a second amount of delay time, the second amount of delay time being shorter than the first amount of delay time, wherein the signal generating means includes: a control means, response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signals include a shift signal, a replication signal and a replication enable signal; a first oscillation means, responsive to the internal clock signal and the delayed internal clock signal, for generating a measurement oscillating signal; and a second oscillation means, responsive to the replication signal and the replication enable signal, for generating a replication oscillating signal.
Claim 3
Dependent Claim
35 words
The delay circuit as recited in claim 1 , wherein the internal clock signal is enabled at a high level from a first rising edge to a second rising edge of the external clock signal.
Claim 4
Dependent Claim
36 words
The delay circuit as recited in claim 2 , wherein the delayed internal clock signal is enabled at a low level from a first rising edge to a second rising edge of the internal clock signal.
Claim 5
Dependent Claim
63 words
The delay circuit as recited in claim 3 , wherein the first delay means includes: a delay measurement unit for shifting a low level of the delayed internal clock signal in response to the measurement oscillating signal and storing the shifted low level; and a delay replication unit for generating the first delay locked clock signal in response to the replication oscillating signal.
Claim 6
Dependent Claim
126 words
The delay circuit as recited in claim 4 , wherein the delay measurement unit includes: a plurality of first transfer control units, responsive to the measurement oscillating signal, for transferring the low level of the delayed internal clock signal to measurement nodes; a plurality of second transfer control units, responsive to a logically combined signal of the delayed internal clock signal, for transferring the low levels of the measurement nodes to the first transfer control units; a bypass register for storing a voltage level of the delayed internal clock signal in response to the internal clock signal and the shift signal; and a plurality of registers for storing the low level of the measurement nodes in response to the internal clock signal and the shift signal.
Claim 7
Dependent Claim
81 words
The delay circuit as recited in claim 5 , wherein each of the registers includes: a first transmission gate for transmitting a voltage level of each measurement node in response to the internal clock signal; a first latch for storing an output signal of the first transmission gate; a second transmission gate for transmitting an output signal of the first latch in response to the shift signal; and a second latch for storing an output signal of the second transmission gate.
Claim 8
Dependent Claim
144 words
The delay circuit as recited in claim 5 , wherein the delay replication means includes: a bypass signal generating unit for generating a bypass signal in response to an output signal of the bypass register and an output signal of a first register; a delay determination unit, responsive to the output signals of the registers, for generating locking signals for determining a degree of delay to be replicated; a plurality of third transfer control units, responsive to the locking signals, the replication signal and the replication oscillating signal, for transferring a predetermined voltage level to the replication nodes; a plurality of fourth transfer control units for transferring each output signal of the third transfer control units to neighboring transfer control unit; and an output unit for outputting the first delay locked clock signal in response to the replication signal and the replication oscillating signal.
Claim 9
Dependent Claim
51 words
The delay circuit as recited in claim 3 , wherein the second delay means includes: a delay measurement unit for measuring a time to be delayed; and a delay replication unit for delaying the first delay locked clock signal for the measurement time to generate the second delay locked clock signal.
Claim 10
Dependent Claim
99 words
The delay circuit as recited in claim 8 , wherein the delay measurement unit includes: a plurality of unit delay elements for delaying the measurement oscillating signal to generate delayed measurement oscillating signals; a plurality of flag registers for storing the delayed measurement oscillating signals in response to the internal clock signal, a flag signal and a shift control signal, wherein the flag signal is provided by the first delay means; and an output unit for receiving signals of the flag registers to generate node signals, each node signal being logically combined with the first delay locked clock signal.
Claim 11
Dependent Claim
122 words
The delay circuit as recited in claim 9 , wherein each flag resister includes: a first transmission gate for transmitting an inverted signal of the delayed measurement oscillating signal in response to the internal clock signal; a first latch for storing an output signal of the first transmission gate; a second transmission gate for transmitting an output signal, of the first latch in response to the shift control signal; a second latch for storing an output signal of the second transmission gate; a third transmission gate for outputting the output signal of the second transmission gate in response to the flag signal; and a fourth transmission gate for outputting a signal stored in the second latch in response to the flag signal.
Claim 12
Dependent Claim
194 words
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model for delaying an external clock signal to generate a delayed clock signal; a signal generation means for generating control signals, an internal clock signal, and a delayed internal clock signal in response to the external clock signal and the delayed clock signal, wherein the signal generation means includes first and second oscillators having the same configuration; a first delay means, responsive to the control signals and to first and second oscillation signals from the first and second oscillators, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means determines an amount of delay time using the first and second oscillation signals and generates a flag signal indicating a first locking; and a second delay means, responsive to the flag signal, the internal clock signal, the shift signal, and the first oscillation signal, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has an amount of delay time smaller than the first delay means.
Claim 13
Dependent Claim
194 words
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model for delaying an external clock signal to generate a delayed clock signal; a signal generation means for generating control signals, an internal clock signal, and a delayed internal clock signal in response to the external clock signal and the delayed clock signal, wherein the signal generation means includes first and second oscillators having the same configuration; a first delay means, responsive to the control signals and to first and second oscillation signals from the first and second oscillators, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means determines an amount of delay time using the first and second oscillation signals and generates a flag signal indicating a first locking; and a second delay means, responsive to the flag signal, the internal clock signal, the shift signal, and the first oscillation signal, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has an amount of delay time smaller than the first delay means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-04 | 2006-05-06 | 2006-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-04 | 2010-05-06 | 2010-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-04 | 2014-05-06 | 2014-11-05 | $7700.00 | Window Closed / Lapsed |