Semiconductor integrated circuit having a DLL circuit and a special power supply circuit for the DLL circuit

Claim 2

A semiconductor integrated circuit having a plurality of elements including a DLL circuit, said DLL circuit receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process, said semiconductor integrated circuit comprising: a power supply circuit keeping a power supply voltage at a specific voltage level and supplying the power supply voltage only to said DLL circuit, wherein said DLL circuit comprises a first delay circuit receiving the first control signal and supplying the second control signal having a specific delay to an object circuit; a divider circuit receiving the first control signal; a second delay circuit receiving a first output signal of said divider circuit; a phase comparator having a first input to which a second output signal of said divider circuit is supplied, and a second input to which an output signal of said second delay circuit is supplied through a delay applying unit, said phase comparator carrying out a comparing process of comparing phases of the second output signal of said divider circuit and the output signal of said second delay circuit, said delay applying unit applying a delay corresponding to a time determined by transferring an output signal of said first delay circuit from said first delay circuit to said object circuit; and a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits.

Claim 3

A semiconductor integrated circuit as claimed in claim 1 , wherein said power supply circuit is a voltage down generator.

Claim 4

A semiconductor integrated circuit as claimed in claim 2 , wherein said voltage down generator comprises a transistor having a first electrode to which the power supply voltage of said semiconductor integrated circuit is applied, a control electrode to which a control voltage is applied, and a second electrode through which an output voltage of said voltage down generator is applied to said DLL circuit.

Claim 5

A semiconductor integrated circuit as claimed in claim 3 , wherein said voltage down generator further comprises a capacitor for maintaining the control voltage applied to the gate of said transistor.

Claim 6

A semiconductor integrated circuit as claimed in claim 1 , wherein said divider circuit generates the first and second output signals by X-dividing a frequency of the first control signal, and the comparing process of said phase comparator is carried out by every X periods of the first control signal, where X denotes an integer number of two or more.

Claim 7

A semiconductor integrated circuit as claimed in claim 5 , wherein the first and second output signals of said divider circuit are complementary signals.

Claim 8

A semiconductor integrated circuit as claimed in claim 5 , wherein said divider circuit generates the first signal where Y periods of the first control signal is at a first level and Z periods of the first control signal is at a second level, and the comparing process of said phase comparator is carried out at a timing of delaying Y periods of the first control signal, where Y denotes an integer number of two or more, and Z denotes an integer number.

Claim 9

A semiconductor integrated circuit as claimed in claim 5 , wherein the first control signal is supplied through an input circuit, and the output signal of said second delay circuit is supplied to the second input of said phase comparator through a dummy line, a dummy object circuit, and a dummy input circuit.

Claim 10

A semiconductor integrated circuit as claimed in claim 8 , wherein a sum of a delay of said input circuit, a minimum delay of said first delay circuit, a delay of said dummy line, and a delay of said object circuit exceeds one period of the first control signal, the comparing process of said phase comparator is carried out by a timing of delaying two or more periods of the first control signal.

Claim 11

A semiconductor integrated circuit as claimed in claim 1 , wherein said semiconductor integrated circuit is a synchronous DRAM, and the object circuit is an output circuit of said synchronous DRAM.

Claim 12

A semiconductor integrated circuit comprising: a DLL circuit receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process; a first power supply circuit keeping a first power supply voltage at a specific voltage level and supplying the first power supply voltage to said DLL circuit; peripheral circuits associated with said DLL circuit; and a second power supply circuit supplying a second power supply voltage to said peripheral circuits, wherein said DLL circuit comprises a first delay circuit receiving the first control signal and supplying the second control signal having a specific delay to an object circuit, a divider circuit receiving the first control signal, a second delay circuit receiving a first output signal of said divider circuit, a phase comparator having a first input to which a second output signal of said divider circuit is supplied, and a second input to which an output signal of said second delay circuit is supplied through a delay applying unit, said phase comparator carrying out a comparing process of comparing phases of the second output signal of said divider circuit and the output signal of said second delay circuit, said delay applying unit applying a delay corresponding to a time determined by transferring an output signal of said first delay circuit from said first delay circuit to said object circuit, and a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits.

Claim 13

A semiconductor integrated circuit comprising: a DLL circuit receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process; a first power supply circuit keeping a first power supply voltage at a specific voltage level and supplying the first power supply voltage to said DLL circuit; peripheral circuits associated with said DLL circuit; and a second power supply circuit supplying a second power supply voltage to said peripheral circuits, wherein said DLL circuit comprises a first delay circuit receiving the first control signal and supplying the second control signal having a specific delay to an object circuit, a divider circuit receiving the first control signal, a second delay circuit receiving a first output signal of said divider circuit, a phase comparator having a first input to which a second output signal of said divider circuit is supplied, and a second input to which an output signal of said second delay circuit is supplied through a delay applying unit, said phase comparator carrying out a comparing process of comparing phases of the second output signal of said divider circuit and the output signal of said second delay circuit, said delay applying unit applying a delay corresponding to a time determined by transferring an output signal of said first delay circuit from said first delay circuit to said object circuit, and a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits.

Claim 14

A semiconductor integrated circuit as claimed in claim 11 , wherein said first power supply circuit is a voltage down generator.

Claim 15

A semiconductor integrated circuit as claimed in claim 12 , wherein said voltage down generator comprises a transistor having a first electrode to which the power supply voltage of said semiconductor integrated circuit is applied, a control electrode to which a control voltage is applied, and a second electrode through which an output voltage of said voltage down generator is applied to said DLL circuit.

Claim 16

A semiconductor integrated circuit as claimed in claim 13 , wherein said voltage down generator further comprises a capacitor for maintaining the control voltage applied to the gate of said transistor.

Claim 17

A semiconductor integrated circuit as claimed in claim 11 , wherein said divider circuit generates the first and second output signals by X-dividing a frequency of the first control signal, and the comparing process of said phase comparator is carried out by every X periods of the first control signal, where X denotes an integer number of two or more.

Claim 18

A semiconductor integrated circuit as claimed in claim 15 , wherein the first and second output signals of said divider circuit are complementary signals.

Claim 19

A semiconductor integrated circuit as claimed in claim 15 , wherein said divider circuit generates the first signal where Y periods of the first control signal is at a first level and Z periods of the first control signal is at a second level, and the comparing process of said phase comparator is carried out at a timing of delaying Y periods of the first control signal, where Y denotes an integer number of two or more, and Z denotes an integer number.

Claim 20

A semiconductor integrated circuit as claimed in claim 15 , wherein the first control signal is supplied through an input circuit, and the output signal of said second delay circuit is supplied to the second input of said phase comparator through a dummy line, a dummy object circuit, and a dummy input circuit.

Claim 21

A semiconductor integrated circuit as claimed in claim 18 , wherein a sum of a delay of said input circuit, a minimum delay of said first delay circuit, a delay of said dummy line, and a delay of said object circuit exceeds one period of the first control signal, the comparing process of said phase comparator is carried out by a timing of delaying two or more periods of the first control signal.

Claim 22

A semiconductor integrated circuit as claimed in claim 11 , wherein said semiconductor integrated circuit is a synchronous DRAM, and the object circuit is an output circuit of said synchronous DRAM.

Claim 23

A semiconductor integrated circuit comprising: a DLL circuit including a first delay circuit receiving a first control signal and supplying a second control signal having a delay time to the first control signal, a second delay circuit coupling to receive the first control signal, a phase comparator having a first input, coupling to receive the first control signal, and a second input coupling to receive an output signal of said second delay circuit, said phase comparator comparing phases of the first control signal and the output signal of said second delay circuit, and a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits; and a power supply circuit keeping a power supply voltage at a specific voltage level and supplying the power supply voltage exclusively to said DLL circuit.

Claim 24

A semiconductor integrated circuit comprising: a DLL circuit including a first delay circuit receiving a first control signal and supplying a second control signal having a delay time to the first control signal, a second delay circuit coupling to receive the first control signal, a phase comparator having a first input, coupling to receive the first control signal, and a second input coupling to receive an output signal of said second delay circuit, said phase comparator comparing phases of the first control signal and the output signal of said second delay circuit, and a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits; and a power supply circuit keeping a power supply voltage at a specific voltage level and supplying the power supply voltage exclusively to said DLL circuit.

Claim 25

A semiconductor integrated circuit comprising: an input buffer circuit receiving an external control signal to supply a first control signal; a DLL circuit receiving the first control signal and generating a second control signal synchronized with the first control signal; a first power supply circuit keeping a first power supply voltage at a specific voltage level and supplying the first power supply voltage exclusively to said DLL circuit; and a second power supply circuit supplying a second power supply voltage to said input buffer circuit, wherein said DLL circuit comprises a first delay circuit receiving the first control signal and supplying the second control signal having a delay time to the first control signal, a second delay circuit coupling to receive the first control signal, a phase comparator having a first input, coupling to receive the first control signal, and a second input, coupling to receive an output signal of said second delay circuit, said phase comparator comparing phases of the first control signal and the output signal of said second delay circuit, and a delay controller receiving a output signal of said phase comparator and controlling delay values of said first and second delay circuits.

Claim 26

A semiconductor integrated circuit comprising: an input buffer circuit receiving an external control signal to supply a first control signal; a DLL circuit receiving the first control signal and generating a second control signal synchronized with the first control signal; a first power supply circuit keeping a first power supply voltage at a specific voltage level and supplying the first power supply voltage exclusively to said DLL circuit; and a second power supply circuit supplying a second power supply voltage to said input buffer circuit, wherein said DLL circuit comprises a first delay circuit receiving the first control signal and supplying the second control signal having a delay time to the first control signal, a second delay circuit coupling to receive the first control signal, a phase comparator having a first input, coupling to receive the first control signal, and a second input, coupling to receive an output signal of said second delay circuit, said phase comparator comparing phases of the first control signal and the output signal of said second delay circuit, and a delay controller receiving a output signal of said phase comparator and controlling delay values of said first and second delay circuits.